source: rtems/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c @ 991fdb33

4.115
Last change on this file since 991fdb33 was ecf64a5e, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 10, 2014 at 2:17:02 PM

bsps/arm: Add a9mpcore_clock_initialize_early()

This is necessary to use the CPU counter converter even in case no clock
driver is present, e.g. in tmcontext01.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp.h>
16#include <bsp/fatal.h>
17#include <bsp/irq.h>
18#include <bsp/arm-a9mpcore-regs.h>
19#include <bsp/arm-a9mpcore-clock.h>
20
21#define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE)
22
23static uint64_t a9mpcore_clock_last_tick_k;
24
25static uint32_t a9mpcore_clock_last_tick_cmpvallower;
26
27static uint32_t a9mpcore_clock_autoinc;
28
29/* This is defined in clockdrv_shell.h */
30void Clock_isr(rtems_irq_hdl_param arg);
31
32__attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void)
33{
34  /* default to the BSP option. */
35  return BSP_ARM_A9MPCORE_PERIPHCLK;
36}
37
38static void a9mpcore_clock_at_tick(void)
39{
40  volatile a9mpcore_gt *gt = A9MPCORE_GT;
41
42  /*
43   * FIXME: Now the _TOD_Get_with_nanoseconds() yields wrong values until
44   * _TOD_Tickle_ticks() managed to update the uptime.  See also PR2180.
45   */
46  a9mpcore_clock_last_tick_cmpvallower =
47    gt->cmpvallower - a9mpcore_clock_autoinc;
48
49  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
50}
51
52static void a9mpcore_clock_handler_install(void)
53{
54  rtems_status_code sc;
55
56  sc = rtems_interrupt_handler_install(
57    A9MPCORE_IRQ_GT,
58    "Clock",
59    RTEMS_INTERRUPT_UNIQUE,
60    (rtems_interrupt_handler) Clock_isr,
61    NULL
62  );
63  if (sc != RTEMS_SUCCESSFUL) {
64    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL);
65  }
66}
67
68static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt)
69{
70  uint32_t cl;
71  uint32_t cu1;
72  uint32_t cu2;
73
74  do {
75    cu1 = gt->cntrupper;
76    cl = gt->cntrlower;
77    cu2 = gt->cntrupper;
78  } while (cu1 != cu2);
79
80  return ((uint64_t) cu2 << 32) | cl;
81}
82
83static void a9mpcore_clock_initialize(void)
84{
85  volatile a9mpcore_gt *gt = A9MPCORE_GT;
86  uint64_t periphclk = a9mpcore_clock_periphclk();
87  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
88  uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000);
89  uint64_t cmpval;
90
91  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
92  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
93
94  cmpval = a9mpcore_clock_get_counter(gt);
95  cmpval += interval;
96
97  gt->cmpvallower = (uint32_t) cmpval;
98  gt->cmpvalupper = (uint32_t) (cmpval >> 32);
99  gt->autoinc = interval;
100
101  a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk;
102  a9mpcore_clock_last_tick_cmpvallower = (uint32_t) cmpval - interval;
103  a9mpcore_clock_autoinc = interval;
104
105  gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN
106    | A9MPCORE_GT_CTRL_IRQ_EN
107    | A9MPCORE_GT_CTRL_COMP_EN
108    | A9MPCORE_GT_CTRL_TMR_EN;
109}
110
111CPU_Counter_ticks _CPU_Counter_read(void)
112{
113  volatile a9mpcore_gt *gt = A9MPCORE_GT;
114
115  return gt->cntrlower;
116}
117
118static void a9mpcore_clock_cleanup_isr(void *arg)
119{
120  volatile a9mpcore_gt *gt = A9MPCORE_GT;
121
122  (void) arg;
123
124  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
125  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
126}
127
128static void a9mpcore_clock_cleanup(void)
129{
130  rtems_status_code sc;
131
132  /*
133   * The relevant registers / bits of the global timer are banked and chances
134   * are on an SPM system, that we are executing on the wrong CPU to reset
135   * them. Thus we will have the actual cleanup done with the next clock tick.
136   * The ISR will execute on the right CPU for the cleanup.
137   */
138  sc = rtems_interrupt_handler_install(
139    A9MPCORE_IRQ_GT,
140    "Clock",
141    RTEMS_INTERRUPT_REPLACE,
142    a9mpcore_clock_cleanup_isr,
143    NULL
144  );
145  if (sc != RTEMS_SUCCESSFUL) {
146    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE);
147  }
148}
149
150static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void)
151{
152  volatile a9mpcore_gt *gt = A9MPCORE_GT;
153  uint64_t k = a9mpcore_clock_last_tick_k;
154  uint32_t n = a9mpcore_clock_last_tick_cmpvallower;
155  uint32_t c = gt->cntrlower;
156
157  return (uint32_t) (((c - n) * k) >> 32);
158}
159
160#define Clock_driver_support_at_tick() \
161  a9mpcore_clock_at_tick()
162
163#define Clock_driver_support_initialize_hardware() \
164  a9mpcore_clock_initialize()
165
166#define Clock_driver_support_install_isr(isr, old_isr) \
167  do { \
168    a9mpcore_clock_handler_install();   \
169    old_isr = NULL; \
170  } while (0)
171
172#define Clock_driver_support_shutdown_hardware() \
173  a9mpcore_clock_cleanup()
174
175#define Clock_driver_nanoseconds_since_last_tick \
176  a9mpcore_clock_nanoseconds_since_last_tick
177
178/* Include shared source clock driver code */
179#include "../../shared/clockdrv_shell.h"
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