source: rtems/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c @ 90d8567

Last change on this file since 90d8567 was 90d8567, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 18, 2016 at 7:36:16 AM

score: Distribute clock tick to all online CPUs

Update #2554.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/*
2 * Copyright (c) 2013, 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp.h>
16#include <bsp/fatal.h>
17#include <bsp/irq.h>
18#include <bsp/irq-generic.h>
19#include <bsp/arm-a9mpcore-regs.h>
20#include <bsp/arm-a9mpcore-clock.h>
21#include <rtems/timecounter.h>
22#include <rtems/score/smpimpl.h>
23
24#define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE)
25
26static struct timecounter a9mpcore_tc;
27
28/* This is defined in clockdrv_shell.h */
29void Clock_isr(rtems_irq_hdl_param arg);
30
31__attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void)
32{
33  /* default to the BSP option. */
34  return BSP_ARM_A9MPCORE_PERIPHCLK;
35}
36
37static void a9mpcore_clock_at_tick(void)
38{
39  volatile a9mpcore_gt *gt = A9MPCORE_GT;
40
41  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
42}
43
44static void a9mpcore_clock_handler_install(void)
45{
46  rtems_status_code sc;
47
48  sc = rtems_interrupt_handler_install(
49    A9MPCORE_IRQ_GT,
50    "Clock",
51    RTEMS_INTERRUPT_UNIQUE,
52    (rtems_interrupt_handler) Clock_isr,
53    NULL
54  );
55  if (sc != RTEMS_SUCCESSFUL) {
56    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL);
57  }
58}
59
60static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt)
61{
62  uint32_t cl;
63  uint32_t cu1;
64  uint32_t cu2;
65
66  do {
67    cu1 = gt->cntrupper;
68    cl = gt->cntrlower;
69    cu2 = gt->cntrupper;
70  } while (cu1 != cu2);
71
72  return ((uint64_t) cu2 << 32) | cl;
73}
74
75static uint32_t a9mpcore_clock_get_timecount(struct timecounter *tc)
76{
77  volatile a9mpcore_gt *gt = A9MPCORE_GT;
78
79  return gt->cntrlower;
80}
81
82static void a9mpcore_clock_gt_init(
83  volatile a9mpcore_gt *gt,
84  uint64_t cmpval,
85  uint32_t interval
86)
87{
88  gt->cmpvallower = (uint32_t) cmpval;
89  gt->cmpvalupper = (uint32_t) (cmpval >> 32);
90  gt->autoinc = interval;
91  gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN
92    | A9MPCORE_GT_CTRL_IRQ_EN
93    | A9MPCORE_GT_CTRL_COMP_EN
94    | A9MPCORE_GT_CTRL_TMR_EN;
95}
96
97#ifdef RTEMS_SMP
98typedef struct {
99  uint64_t cmpval;
100  uint32_t interval;
101} a9mpcore_clock_init_data;
102
103static void a9mpcore_clock_secondary_action(void *arg)
104{
105  volatile a9mpcore_gt *gt = A9MPCORE_GT;
106  a9mpcore_clock_init_data *init_data = arg;
107
108  a9mpcore_clock_gt_init(gt, init_data->cmpval, init_data->interval);
109  bsp_interrupt_vector_enable(A9MPCORE_IRQ_GT);
110}
111#endif
112
113static void a9mpcore_clock_secondary_initialization(
114  volatile a9mpcore_gt *gt,
115  uint64_t cmpval,
116  uint32_t interval
117)
118{
119#ifdef RTEMS_SMP
120  a9mpcore_clock_init_data init_data = {
121    .cmpval = cmpval,
122    .interval = interval
123  };
124
125  _SMP_Before_multitasking_action_broadcast(
126    a9mpcore_clock_secondary_action,
127    &init_data
128  );
129
130  if (cmpval - a9mpcore_clock_get_counter(gt) >= interval) {
131    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_SMP_INIT);
132  }
133#endif
134}
135
136static void a9mpcore_clock_initialize(void)
137{
138  volatile a9mpcore_gt *gt = A9MPCORE_GT;
139  uint64_t periphclk = a9mpcore_clock_periphclk();
140  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
141  uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000);
142  uint64_t cmpval;
143
144  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
145  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
146
147  cmpval = a9mpcore_clock_get_counter(gt);
148  cmpval += interval;
149
150  a9mpcore_clock_gt_init(gt, cmpval, interval);
151  a9mpcore_clock_secondary_initialization(gt, cmpval, interval);
152
153  a9mpcore_tc.tc_get_timecount = a9mpcore_clock_get_timecount;
154  a9mpcore_tc.tc_counter_mask = 0xffffffff;
155  a9mpcore_tc.tc_frequency = periphclk;
156  a9mpcore_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
157  rtems_timecounter_install(&a9mpcore_tc);
158}
159
160CPU_Counter_ticks _CPU_Counter_read(void)
161{
162  volatile a9mpcore_gt *gt = A9MPCORE_GT;
163
164  return gt->cntrlower;
165}
166
167static void a9mpcore_clock_cleanup_isr(void *arg)
168{
169  volatile a9mpcore_gt *gt = A9MPCORE_GT;
170
171  (void) arg;
172
173  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
174  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
175}
176
177static void a9mpcore_clock_cleanup(void)
178{
179  rtems_status_code sc;
180
181  /*
182   * The relevant registers / bits of the global timer are banked and chances
183   * are on an SPM system, that we are executing on the wrong CPU to reset
184   * them. Thus we will have the actual cleanup done with the next clock tick.
185   * The ISR will execute on the right CPU for the cleanup.
186   */
187  sc = rtems_interrupt_handler_install(
188    A9MPCORE_IRQ_GT,
189    "Clock",
190    RTEMS_INTERRUPT_REPLACE,
191    a9mpcore_clock_cleanup_isr,
192    NULL
193  );
194  if (sc != RTEMS_SUCCESSFUL) {
195    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE);
196  }
197}
198
199#define Clock_driver_support_at_tick() \
200  a9mpcore_clock_at_tick()
201
202#define Clock_driver_support_initialize_hardware() \
203  a9mpcore_clock_initialize()
204
205#define Clock_driver_support_install_isr(isr, old_isr) \
206  do { \
207    a9mpcore_clock_handler_install(); \
208    old_isr = NULL; \
209  } while (0)
210
211#define Clock_driver_support_shutdown_hardware() \
212  a9mpcore_clock_cleanup()
213
214/* Include shared source clock driver code */
215#include "../../shared/clockdrv_shell.h"
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