1 | /* |
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2 | * Copyright (c) 2013-2015 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/fatal.h> |
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17 | #include <bsp/irq.h> |
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18 | #include <bsp/arm-a9mpcore-regs.h> |
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19 | #include <bsp/arm-a9mpcore-clock.h> |
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20 | #include <rtems/timecounter.h> |
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21 | |
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22 | #define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE) |
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23 | |
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24 | static struct timecounter a9mpcore_tc; |
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25 | |
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26 | /* This is defined in clockdrv_shell.h */ |
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27 | void Clock_isr(rtems_irq_hdl_param arg); |
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28 | |
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29 | __attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void) |
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30 | { |
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31 | /* default to the BSP option. */ |
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32 | return BSP_ARM_A9MPCORE_PERIPHCLK; |
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33 | } |
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34 | |
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35 | static void a9mpcore_clock_at_tick(void) |
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36 | { |
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37 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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38 | |
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39 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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40 | } |
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41 | |
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42 | static void a9mpcore_clock_handler_install(void) |
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43 | { |
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44 | rtems_status_code sc; |
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45 | |
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46 | sc = rtems_interrupt_handler_install( |
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47 | A9MPCORE_IRQ_GT, |
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48 | "Clock", |
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49 | RTEMS_INTERRUPT_UNIQUE, |
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50 | (rtems_interrupt_handler) Clock_isr, |
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51 | NULL |
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52 | ); |
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53 | if (sc != RTEMS_SUCCESSFUL) { |
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54 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL); |
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55 | } |
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56 | } |
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57 | |
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58 | static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt) |
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59 | { |
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60 | uint32_t cl; |
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61 | uint32_t cu1; |
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62 | uint32_t cu2; |
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63 | |
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64 | do { |
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65 | cu1 = gt->cntrupper; |
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66 | cl = gt->cntrlower; |
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67 | cu2 = gt->cntrupper; |
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68 | } while (cu1 != cu2); |
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69 | |
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70 | return ((uint64_t) cu2 << 32) | cl; |
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71 | } |
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72 | |
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73 | static uint32_t a9mpcore_clock_get_timecount(struct timecounter *tc) |
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74 | { |
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75 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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76 | |
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77 | return gt->cntrlower; |
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78 | } |
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79 | |
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80 | static void a9mpcore_clock_initialize(void) |
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81 | { |
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82 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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83 | uint64_t periphclk = a9mpcore_clock_periphclk(); |
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84 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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85 | uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000); |
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86 | uint64_t cmpval; |
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87 | |
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88 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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89 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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90 | |
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91 | cmpval = a9mpcore_clock_get_counter(gt); |
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92 | cmpval += interval; |
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93 | |
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94 | gt->cmpvallower = (uint32_t) cmpval; |
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95 | gt->cmpvalupper = (uint32_t) (cmpval >> 32); |
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96 | gt->autoinc = interval; |
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97 | |
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98 | gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN |
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99 | | A9MPCORE_GT_CTRL_IRQ_EN |
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100 | | A9MPCORE_GT_CTRL_COMP_EN |
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101 | | A9MPCORE_GT_CTRL_TMR_EN; |
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102 | |
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103 | a9mpcore_tc.tc_get_timecount = a9mpcore_clock_get_timecount; |
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104 | a9mpcore_tc.tc_counter_mask = 0xffffffff; |
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105 | a9mpcore_tc.tc_frequency = periphclk; |
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106 | a9mpcore_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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107 | rtems_timecounter_install(&a9mpcore_tc); |
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108 | } |
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109 | |
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110 | CPU_Counter_ticks _CPU_Counter_read(void) |
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111 | { |
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112 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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113 | |
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114 | return gt->cntrlower; |
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115 | } |
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116 | |
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117 | static void a9mpcore_clock_cleanup_isr(void *arg) |
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118 | { |
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119 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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120 | |
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121 | (void) arg; |
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122 | |
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123 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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124 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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125 | } |
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126 | |
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127 | static void a9mpcore_clock_cleanup(void) |
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128 | { |
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129 | rtems_status_code sc; |
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130 | |
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131 | /* |
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132 | * The relevant registers / bits of the global timer are banked and chances |
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133 | * are on an SPM system, that we are executing on the wrong CPU to reset |
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134 | * them. Thus we will have the actual cleanup done with the next clock tick. |
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135 | * The ISR will execute on the right CPU for the cleanup. |
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136 | */ |
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137 | sc = rtems_interrupt_handler_install( |
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138 | A9MPCORE_IRQ_GT, |
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139 | "Clock", |
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140 | RTEMS_INTERRUPT_REPLACE, |
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141 | a9mpcore_clock_cleanup_isr, |
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142 | NULL |
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143 | ); |
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144 | if (sc != RTEMS_SUCCESSFUL) { |
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145 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE); |
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146 | } |
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147 | } |
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148 | |
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149 | #define Clock_driver_support_at_tick() \ |
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150 | a9mpcore_clock_at_tick() |
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151 | |
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152 | #define Clock_driver_support_initialize_hardware() \ |
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153 | a9mpcore_clock_initialize() |
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154 | |
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155 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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156 | do { \ |
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157 | a9mpcore_clock_handler_install(); \ |
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158 | old_isr = NULL; \ |
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159 | } while (0) |
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160 | |
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161 | #define Clock_driver_support_shutdown_hardware() \ |
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162 | a9mpcore_clock_cleanup() |
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163 | |
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164 | /* Include shared source clock driver code */ |
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165 | #include "../../shared/clockdrv_shell.h" |
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