[a91dc98b] | 1 | /* |
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[0df8d7f2] | 2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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[a91dc98b] | 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[a91dc98b] | 13 | */ |
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| 14 | |
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[24bf11e] | 15 | #include <rtems/counter.h> |
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| 16 | |
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[a91dc98b] | 17 | #include <bsp.h> |
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[33cb8bf] | 18 | #include <bsp/fatal.h> |
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[a91dc98b] | 19 | #include <bsp/irq.h> |
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| 20 | #include <bsp/arm-a9mpcore-regs.h> |
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[069e10c3] | 21 | #include <bsp/arm-a9mpcore-clock.h> |
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[a91dc98b] | 22 | |
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[0df8d7f2] | 23 | #define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE) |
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[a91dc98b] | 24 | |
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[f466e56] | 25 | static uint64_t a9mpcore_clock_last_tick_k; |
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| 26 | |
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[c19342a7] | 27 | static uint32_t a9mpcore_clock_last_tick_cmpvallower; |
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| 28 | |
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| 29 | static uint32_t a9mpcore_clock_autoinc; |
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| 30 | |
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[a91dc98b] | 31 | /* This is defined in clockdrv_shell.h */ |
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| 32 | void Clock_isr(rtems_irq_hdl_param arg); |
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| 33 | |
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[069e10c3] | 34 | __attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void) |
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[f466e56] | 35 | { |
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| 36 | /* default to the BSP option. */ |
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| 37 | return BSP_ARM_A9MPCORE_PERIPHCLK; |
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| 38 | } |
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| 39 | |
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[a91dc98b] | 40 | static void a9mpcore_clock_at_tick(void) |
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| 41 | { |
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[0df8d7f2] | 42 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[a91dc98b] | 43 | |
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[c19342a7] | 44 | /* |
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| 45 | * FIXME: Now the _TOD_Get_with_nanoseconds() yields wrong values until |
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| 46 | * _TOD_Tickle_ticks() managed to update the uptime. See also PR2180. |
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| 47 | */ |
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| 48 | a9mpcore_clock_last_tick_cmpvallower = |
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| 49 | gt->cmpvallower - a9mpcore_clock_autoinc; |
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| 50 | |
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[0df8d7f2] | 51 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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[a91dc98b] | 52 | } |
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| 53 | |
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| 54 | static void a9mpcore_clock_handler_install(void) |
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| 55 | { |
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| 56 | rtems_status_code sc; |
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| 57 | |
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| 58 | sc = rtems_interrupt_handler_install( |
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[0df8d7f2] | 59 | A9MPCORE_IRQ_GT, |
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[a91dc98b] | 60 | "Clock", |
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| 61 | RTEMS_INTERRUPT_UNIQUE, |
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| 62 | (rtems_interrupt_handler) Clock_isr, |
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| 63 | NULL |
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| 64 | ); |
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| 65 | if (sc != RTEMS_SUCCESSFUL) { |
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[33cb8bf] | 66 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL); |
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[a91dc98b] | 67 | } |
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| 68 | } |
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| 69 | |
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[0df8d7f2] | 70 | static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt) |
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[a91dc98b] | 71 | { |
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[0df8d7f2] | 72 | uint32_t cl; |
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| 73 | uint32_t cu1; |
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| 74 | uint32_t cu2; |
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| 75 | |
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| 76 | do { |
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| 77 | cu1 = gt->cntrupper; |
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| 78 | cl = gt->cntrlower; |
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| 79 | cu2 = gt->cntrupper; |
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| 80 | } while (cu1 != cu2); |
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[a91dc98b] | 81 | |
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[0df8d7f2] | 82 | return ((uint64_t) cu2 << 32) | cl; |
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| 83 | } |
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[f466e56] | 84 | |
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[0df8d7f2] | 85 | static void a9mpcore_clock_initialize(void) |
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| 86 | { |
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| 87 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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| 88 | uint64_t periphclk = a9mpcore_clock_periphclk(); |
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| 89 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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| 90 | uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000); |
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| 91 | uint64_t cmpval; |
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| 92 | |
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| 93 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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| 94 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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| 95 | |
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| 96 | cmpval = a9mpcore_clock_get_counter(gt); |
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| 97 | cmpval += interval; |
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| 98 | |
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| 99 | gt->cmpvallower = (uint32_t) cmpval; |
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| 100 | gt->cmpvalupper = (uint32_t) (cmpval >> 32); |
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| 101 | gt->autoinc = interval; |
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[c19342a7] | 102 | |
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| 103 | a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk; |
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| 104 | a9mpcore_clock_last_tick_cmpvallower = (uint32_t) cmpval - interval; |
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| 105 | a9mpcore_clock_autoinc = interval; |
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| 106 | |
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[0df8d7f2] | 107 | gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN |
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| 108 | | A9MPCORE_GT_CTRL_IRQ_EN |
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| 109 | | A9MPCORE_GT_CTRL_COMP_EN |
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| 110 | | A9MPCORE_GT_CTRL_TMR_EN; |
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[24bf11e] | 111 | |
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| 112 | rtems_counter_initialize_converter((uint32_t) periphclk); |
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| 113 | } |
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| 114 | |
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| 115 | CPU_Counter_ticks _CPU_Counter_read(void) |
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| 116 | { |
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| 117 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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| 118 | |
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| 119 | return gt->cntrlower; |
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[a91dc98b] | 120 | } |
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| 121 | |
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[34568acf] | 122 | static void a9mpcore_clock_cleanup_isr(void *arg) |
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[a91dc98b] | 123 | { |
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[0df8d7f2] | 124 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[34568acf] | 125 | |
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| 126 | (void) arg; |
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[a91dc98b] | 127 | |
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[0df8d7f2] | 128 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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| 129 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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[34568acf] | 130 | } |
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[a91dc98b] | 131 | |
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[34568acf] | 132 | static void a9mpcore_clock_cleanup(void) |
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| 133 | { |
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| 134 | rtems_status_code sc; |
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| 135 | |
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| 136 | /* |
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| 137 | * The relevant registers / bits of the global timer are banked and chances |
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| 138 | * are on an SPM system, that we are executing on the wrong CPU to reset |
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| 139 | * them. Thus we will have the actual cleanup done with the next clock tick. |
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| 140 | * The ISR will execute on the right CPU for the cleanup. |
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| 141 | */ |
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| 142 | sc = rtems_interrupt_handler_install( |
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[0df8d7f2] | 143 | A9MPCORE_IRQ_GT, |
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[34568acf] | 144 | "Clock", |
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| 145 | RTEMS_INTERRUPT_REPLACE, |
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| 146 | a9mpcore_clock_cleanup_isr, |
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[a91dc98b] | 147 | NULL |
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| 148 | ); |
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| 149 | if (sc != RTEMS_SUCCESSFUL) { |
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[33cb8bf] | 150 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE); |
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[a91dc98b] | 151 | } |
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| 152 | } |
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| 153 | |
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| 154 | static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void) |
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| 155 | { |
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[0df8d7f2] | 156 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[f466e56] | 157 | uint64_t k = a9mpcore_clock_last_tick_k; |
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[c19342a7] | 158 | uint32_t n = a9mpcore_clock_last_tick_cmpvallower; |
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[0df8d7f2] | 159 | uint32_t c = gt->cntrlower; |
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[a91dc98b] | 160 | |
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[c19342a7] | 161 | return (uint32_t) (((c - n) * k) >> 32); |
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[a91dc98b] | 162 | } |
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| 163 | |
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| 164 | #define Clock_driver_support_at_tick() \ |
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| 165 | a9mpcore_clock_at_tick() |
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| 166 | |
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| 167 | #define Clock_driver_support_initialize_hardware() \ |
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| 168 | a9mpcore_clock_initialize() |
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| 169 | |
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| 170 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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| 171 | do { \ |
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| 172 | a9mpcore_clock_handler_install(); \ |
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| 173 | old_isr = NULL; \ |
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| 174 | } while (0) |
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| 175 | |
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| 176 | #define Clock_driver_support_shutdown_hardware() \ |
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| 177 | a9mpcore_clock_cleanup() |
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| 178 | |
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| 179 | #define Clock_driver_nanoseconds_since_last_tick \ |
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| 180 | a9mpcore_clock_nanoseconds_since_last_tick |
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| 181 | |
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| 182 | /* Include shared source clock driver code */ |
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| 183 | #include "../../shared/clockdrv_shell.h" |
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