[a91dc98b] | 1 | /* |
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| 2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #include <bsp.h> |
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| 16 | #include <bsp/irq.h> |
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| 17 | #include <bsp/arm-a9mpcore-regs.h> |
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| 18 | |
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| 19 | #define A9MPCORE_PT ((volatile a9mpcore_pt *) BSP_ARM_A9MPCORE_PT_BASE) |
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| 20 | |
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| 21 | /* This is defined in clockdrv_shell.h */ |
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| 22 | void Clock_isr(rtems_irq_hdl_param arg); |
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| 23 | |
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| 24 | static void a9mpcore_clock_at_tick(void) |
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| 25 | { |
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| 26 | volatile a9mpcore_pt *pt = A9MPCORE_PT; |
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| 27 | |
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| 28 | pt->irqst = A9MPCORE_PT_IRQST_EFLG; |
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| 29 | } |
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| 30 | |
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| 31 | static void a9mpcore_clock_handler_install(void) |
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| 32 | { |
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| 33 | rtems_status_code sc; |
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| 34 | |
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| 35 | sc = rtems_interrupt_handler_install( |
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| 36 | A9MPCORE_IRQ_PT, |
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| 37 | "Clock", |
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| 38 | RTEMS_INTERRUPT_UNIQUE, |
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| 39 | (rtems_interrupt_handler) Clock_isr, |
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| 40 | NULL |
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| 41 | ); |
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| 42 | if (sc != RTEMS_SUCCESSFUL) { |
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| 43 | rtems_fatal( |
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| 44 | RTEMS_FATAL_SOURCE_BSP_SPECIFIC, |
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| 45 | BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL |
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| 46 | ); |
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| 47 | } |
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| 48 | } |
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| 49 | |
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| 50 | static void a9mpcore_clock_initialize(void) |
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| 51 | { |
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| 52 | volatile a9mpcore_pt *pt = A9MPCORE_PT; |
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| 53 | uint64_t interval = ((uint64_t) BSP_ARM_A9MPCORE_PERIPHCLK |
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| 54 | * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000; |
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| 55 | |
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| 56 | pt->load = (uint32_t) interval - 1; |
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| 57 | pt->ctrl = A9MPCORE_PT_CTRL_AUTO_RLD |
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| 58 | | A9MPCORE_PT_CTRL_IRQ_EN |
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| 59 | | A9MPCORE_PT_CTRL_TMR_EN; |
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| 60 | } |
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| 61 | |
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| 62 | static void a9mpcore_clock_cleanup(void) |
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| 63 | { |
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| 64 | volatile a9mpcore_pt *pt = A9MPCORE_PT; |
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| 65 | rtems_status_code sc; |
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| 66 | |
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| 67 | pt->ctrl = 0; |
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| 68 | pt->irqst = A9MPCORE_PT_IRQST_EFLG; |
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| 69 | |
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| 70 | sc = rtems_interrupt_handler_remove( |
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| 71 | A9MPCORE_IRQ_PT, |
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| 72 | (rtems_interrupt_handler) Clock_isr, |
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| 73 | NULL |
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| 74 | ); |
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| 75 | if (sc != RTEMS_SUCCESSFUL) { |
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| 76 | rtems_fatal( |
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| 77 | RTEMS_FATAL_SOURCE_BSP_SPECIFIC, |
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| 78 | BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE |
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| 79 | ); |
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| 80 | } |
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| 81 | } |
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| 82 | |
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| 83 | static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void) |
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| 84 | { |
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| 85 | volatile a9mpcore_pt *pt = A9MPCORE_PT; |
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| 86 | uint64_t k = (1000000000ULL << 32) / BSP_ARM_A9MPCORE_PERIPHCLK; |
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| 87 | uint32_t c = pt->cntr; |
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| 88 | uint32_t p = pt->load + 1; |
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| 89 | |
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| 90 | if ((pt->irqst & A9MPCORE_PT_IRQST_EFLG) != 0) { |
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| 91 | c = pt->cntr + p; |
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| 92 | } |
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| 93 | |
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| 94 | return (uint32_t) (((p - c) * k) >> 32); |
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| 95 | } |
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| 96 | |
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| 97 | #define Clock_driver_support_at_tick() \ |
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| 98 | a9mpcore_clock_at_tick() |
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| 99 | |
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| 100 | #define Clock_driver_support_initialize_hardware() \ |
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| 101 | a9mpcore_clock_initialize() |
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| 102 | |
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| 103 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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| 104 | do { \ |
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| 105 | a9mpcore_clock_handler_install(); \ |
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| 106 | old_isr = NULL; \ |
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| 107 | } while (0) |
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| 108 | |
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| 109 | #define Clock_driver_support_shutdown_hardware() \ |
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| 110 | a9mpcore_clock_cleanup() |
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| 111 | |
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| 112 | #define Clock_driver_nanoseconds_since_last_tick \ |
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| 113 | a9mpcore_clock_nanoseconds_since_last_tick |
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| 114 | |
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| 115 | /* Include shared source clock driver code */ |
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| 116 | #include "../../shared/clockdrv_shell.h" |
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