[a91dc98b] | 1 | /* |
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[0df8d7f2] | 2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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[a91dc98b] | 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[a91dc98b] | 13 | */ |
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| 14 | |
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| 15 | #include <bsp.h> |
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[33cb8bf] | 16 | #include <bsp/fatal.h> |
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[a91dc98b] | 17 | #include <bsp/irq.h> |
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| 18 | #include <bsp/arm-a9mpcore-regs.h> |
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[069e10c3] | 19 | #include <bsp/arm-a9mpcore-clock.h> |
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[a91dc98b] | 20 | |
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[0df8d7f2] | 21 | #define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE) |
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[a91dc98b] | 22 | |
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[f466e56] | 23 | static uint64_t a9mpcore_clock_last_tick_k; |
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| 24 | |
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[c19342a7] | 25 | static uint32_t a9mpcore_clock_last_tick_cmpvallower; |
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| 26 | |
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| 27 | static uint32_t a9mpcore_clock_autoinc; |
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| 28 | |
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[a91dc98b] | 29 | /* This is defined in clockdrv_shell.h */ |
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| 30 | void Clock_isr(rtems_irq_hdl_param arg); |
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| 31 | |
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[069e10c3] | 32 | __attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void) |
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[f466e56] | 33 | { |
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| 34 | /* default to the BSP option. */ |
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| 35 | return BSP_ARM_A9MPCORE_PERIPHCLK; |
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| 36 | } |
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| 37 | |
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[a91dc98b] | 38 | static void a9mpcore_clock_at_tick(void) |
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| 39 | { |
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[0df8d7f2] | 40 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[a91dc98b] | 41 | |
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[c19342a7] | 42 | /* |
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| 43 | * FIXME: Now the _TOD_Get_with_nanoseconds() yields wrong values until |
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| 44 | * _TOD_Tickle_ticks() managed to update the uptime. See also PR2180. |
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| 45 | */ |
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| 46 | a9mpcore_clock_last_tick_cmpvallower = |
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| 47 | gt->cmpvallower - a9mpcore_clock_autoinc; |
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| 48 | |
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[0df8d7f2] | 49 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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[a91dc98b] | 50 | } |
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| 51 | |
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| 52 | static void a9mpcore_clock_handler_install(void) |
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| 53 | { |
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| 54 | rtems_status_code sc; |
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| 55 | |
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| 56 | sc = rtems_interrupt_handler_install( |
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[0df8d7f2] | 57 | A9MPCORE_IRQ_GT, |
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[a91dc98b] | 58 | "Clock", |
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| 59 | RTEMS_INTERRUPT_UNIQUE, |
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| 60 | (rtems_interrupt_handler) Clock_isr, |
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| 61 | NULL |
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| 62 | ); |
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| 63 | if (sc != RTEMS_SUCCESSFUL) { |
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[33cb8bf] | 64 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL); |
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[a91dc98b] | 65 | } |
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| 66 | } |
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| 67 | |
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[0df8d7f2] | 68 | static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt) |
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[a91dc98b] | 69 | { |
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[0df8d7f2] | 70 | uint32_t cl; |
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| 71 | uint32_t cu1; |
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| 72 | uint32_t cu2; |
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| 73 | |
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| 74 | do { |
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| 75 | cu1 = gt->cntrupper; |
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| 76 | cl = gt->cntrlower; |
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| 77 | cu2 = gt->cntrupper; |
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| 78 | } while (cu1 != cu2); |
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[a91dc98b] | 79 | |
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[0df8d7f2] | 80 | return ((uint64_t) cu2 << 32) | cl; |
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| 81 | } |
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[f466e56] | 82 | |
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[0df8d7f2] | 83 | static void a9mpcore_clock_initialize(void) |
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| 84 | { |
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| 85 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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| 86 | uint64_t periphclk = a9mpcore_clock_periphclk(); |
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| 87 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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| 88 | uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000); |
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| 89 | uint64_t cmpval; |
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| 90 | |
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| 91 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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| 92 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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| 93 | |
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| 94 | cmpval = a9mpcore_clock_get_counter(gt); |
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| 95 | cmpval += interval; |
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| 96 | |
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| 97 | gt->cmpvallower = (uint32_t) cmpval; |
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| 98 | gt->cmpvalupper = (uint32_t) (cmpval >> 32); |
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| 99 | gt->autoinc = interval; |
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[c19342a7] | 100 | |
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| 101 | a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk; |
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| 102 | a9mpcore_clock_last_tick_cmpvallower = (uint32_t) cmpval - interval; |
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| 103 | a9mpcore_clock_autoinc = interval; |
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| 104 | |
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[0df8d7f2] | 105 | gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN |
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| 106 | | A9MPCORE_GT_CTRL_IRQ_EN |
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| 107 | | A9MPCORE_GT_CTRL_COMP_EN |
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| 108 | | A9MPCORE_GT_CTRL_TMR_EN; |
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[24bf11e] | 109 | } |
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| 110 | |
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| 111 | CPU_Counter_ticks _CPU_Counter_read(void) |
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| 112 | { |
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| 113 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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| 114 | |
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| 115 | return gt->cntrlower; |
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[a91dc98b] | 116 | } |
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| 117 | |
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[34568acf] | 118 | static void a9mpcore_clock_cleanup_isr(void *arg) |
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[a91dc98b] | 119 | { |
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[0df8d7f2] | 120 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[34568acf] | 121 | |
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| 122 | (void) arg; |
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[a91dc98b] | 123 | |
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[0df8d7f2] | 124 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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| 125 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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[34568acf] | 126 | } |
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[a91dc98b] | 127 | |
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[34568acf] | 128 | static void a9mpcore_clock_cleanup(void) |
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| 129 | { |
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| 130 | rtems_status_code sc; |
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| 131 | |
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| 132 | /* |
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| 133 | * The relevant registers / bits of the global timer are banked and chances |
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| 134 | * are on an SPM system, that we are executing on the wrong CPU to reset |
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| 135 | * them. Thus we will have the actual cleanup done with the next clock tick. |
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| 136 | * The ISR will execute on the right CPU for the cleanup. |
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| 137 | */ |
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| 138 | sc = rtems_interrupt_handler_install( |
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[0df8d7f2] | 139 | A9MPCORE_IRQ_GT, |
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[34568acf] | 140 | "Clock", |
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| 141 | RTEMS_INTERRUPT_REPLACE, |
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| 142 | a9mpcore_clock_cleanup_isr, |
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[a91dc98b] | 143 | NULL |
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| 144 | ); |
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| 145 | if (sc != RTEMS_SUCCESSFUL) { |
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[33cb8bf] | 146 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE); |
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[a91dc98b] | 147 | } |
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| 148 | } |
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| 149 | |
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| 150 | static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void) |
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| 151 | { |
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[0df8d7f2] | 152 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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[f466e56] | 153 | uint64_t k = a9mpcore_clock_last_tick_k; |
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[c19342a7] | 154 | uint32_t n = a9mpcore_clock_last_tick_cmpvallower; |
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[0df8d7f2] | 155 | uint32_t c = gt->cntrlower; |
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[a91dc98b] | 156 | |
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[c19342a7] | 157 | return (uint32_t) (((c - n) * k) >> 32); |
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[a91dc98b] | 158 | } |
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| 159 | |
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| 160 | #define Clock_driver_support_at_tick() \ |
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| 161 | a9mpcore_clock_at_tick() |
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| 162 | |
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| 163 | #define Clock_driver_support_initialize_hardware() \ |
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| 164 | a9mpcore_clock_initialize() |
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| 165 | |
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| 166 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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| 167 | do { \ |
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| 168 | a9mpcore_clock_handler_install(); \ |
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| 169 | old_isr = NULL; \ |
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| 170 | } while (0) |
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| 171 | |
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| 172 | #define Clock_driver_support_shutdown_hardware() \ |
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| 173 | a9mpcore_clock_cleanup() |
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| 174 | |
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| 175 | #define Clock_driver_nanoseconds_since_last_tick \ |
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| 176 | a9mpcore_clock_nanoseconds_since_last_tick |
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| 177 | |
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| 178 | /* Include shared source clock driver code */ |
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| 179 | #include "../../shared/clockdrv_shell.h" |
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