1 | /* |
---|
2 | * ARM CPU Dependent Source |
---|
3 | * |
---|
4 | * COPYRIGHT (c) 2007 Ray Xu. |
---|
5 | * mailto: Rayx at gmail dot com |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
---|
8 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
---|
9 | * |
---|
10 | * Copyright (c) 2002 Advent Networks, Inc |
---|
11 | * Jay Monkman <jmonkman@adventnetworks.com> |
---|
12 | * |
---|
13 | * If you want a small footprint RTEMS, pls use simple_abort.c |
---|
14 | * |
---|
15 | * The license and distribution terms for this file may be |
---|
16 | * found in the file LICENSE in this distribution or at |
---|
17 | * http://www.rtems.com/license/LICENSE. |
---|
18 | * |
---|
19 | */ |
---|
20 | |
---|
21 | #include <rtems/system.h> |
---|
22 | #include <rtems.h> |
---|
23 | #include <rtems/bspIo.h> |
---|
24 | |
---|
25 | #define INSN_MASK 0xc5 |
---|
26 | |
---|
27 | #define INSN_STM1 0x80 |
---|
28 | #define INSN_STM2 0x84 |
---|
29 | #define INSN_STR 0x40 |
---|
30 | #define INSN_STRB 0x44 |
---|
31 | |
---|
32 | #define INSN_LDM1 0x81 |
---|
33 | #define INSN_LDM23 0x85 |
---|
34 | #define INSN_LDR 0x41 |
---|
35 | #define INSN_LDRB 0x45 |
---|
36 | |
---|
37 | #define GET_RD(x) ((x & 0x0000f000) >> 12) |
---|
38 | #define GET_RN(x) ((x & 0x000f0000) >> 16) |
---|
39 | |
---|
40 | #define GET_U(x) ((x & 0x00800000) >> 23) |
---|
41 | #define GET_I(x) ((x & 0x02000000) >> 25) |
---|
42 | |
---|
43 | #define GET_REG(r, ctx) (((uint32_t *)ctx)[r]) |
---|
44 | #define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v) |
---|
45 | #define GET_OFFSET(insn) (insn & 0xfff) |
---|
46 | |
---|
47 | uint32_t g_data_abort_cnt = 0; |
---|
48 | /*this is a big overhead for MCU only got 16K RAM*/ |
---|
49 | uint32_t g_data_abort_insn_list[1024]; |
---|
50 | |
---|
51 | |
---|
52 | char *_print_full_context_mode2txt[0x20]={ |
---|
53 | [0x0]="user", /* User */ |
---|
54 | [0x1]="fiq", /* FIQ - Fast Interrupt Request */ |
---|
55 | [0x2]="irq", /* IRQ - Interrupt Request */ |
---|
56 | [0x3]="super", /* Supervisor */ |
---|
57 | [0x7]="abort", /* Abort */ |
---|
58 | [0xb]="undef", /* Undefined */ |
---|
59 | [0xf]="system" /* System */ |
---|
60 | }; |
---|
61 | |
---|
62 | |
---|
63 | void _print_full_context(uint32_t spsr) |
---|
64 | { |
---|
65 | char *mode; |
---|
66 | uint32_t prev_sp,prev_lr,cpsr,tmp; |
---|
67 | int i; |
---|
68 | |
---|
69 | printk("active thread thread 0x%08x\n", _Thread_Executing->Object.id); |
---|
70 | |
---|
71 | mode=_print_full_context_mode2txt[spsr&0x1f]; |
---|
72 | if(!mode) mode="unknown"; |
---|
73 | |
---|
74 | asm volatile (" MRS %[cpsr], cpsr \n" |
---|
75 | " ORR %[tmp], %[spsr], #0xc0 \n" |
---|
76 | " MSR cpsr_c, %[tmp] \n" |
---|
77 | " MOV %[prev_sp], sp \n" |
---|
78 | " MOV %[prev_lr], lr \n" |
---|
79 | " MSR cpsr_c, %[cpsr] \n" |
---|
80 | : [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr), |
---|
81 | [cpsr] "=&r" (cpsr), [tmp] "=&r" (tmp) |
---|
82 | : [spsr] "r" (spsr) |
---|
83 | : "cc"); |
---|
84 | |
---|
85 | printk("Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n", |
---|
86 | prev_sp, prev_lr, cpsr); |
---|
87 | |
---|
88 | for(i=0;i<48;){ |
---|
89 | printk(" 0x%08x",((uint32_t*)prev_sp)[i++]); |
---|
90 | if((i%6) == 0) |
---|
91 | printk("\n"); |
---|
92 | } |
---|
93 | |
---|
94 | } |
---|
95 | |
---|
96 | |
---|
97 | /* This function is supposed to figure out what caused the |
---|
98 | * data abort, do that, then return. |
---|
99 | * |
---|
100 | * All unhandled instructions cause the system to hang. |
---|
101 | */ |
---|
102 | |
---|
103 | void do_data_abort(uint32_t insn, uint32_t spsr, |
---|
104 | Context_Control *ctx) |
---|
105 | { |
---|
106 | /* Clarify, which type is correct, CPU_Exception_frame or Context_Control */ |
---|
107 | uint8_t decode; |
---|
108 | uint8_t insn_type; |
---|
109 | rtems_interrupt_level level; |
---|
110 | |
---|
111 | g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8; |
---|
112 | g_data_abort_cnt++; |
---|
113 | |
---|
114 | decode = ((insn >> 20) & 0xff); |
---|
115 | |
---|
116 | insn_type = decode & INSN_MASK; |
---|
117 | switch(insn_type) { |
---|
118 | case INSN_STM1: |
---|
119 | printk("\n\nINSN_STM1\n"); |
---|
120 | break; |
---|
121 | case INSN_STM2: |
---|
122 | printk("\n\nINSN_STM2\n"); |
---|
123 | break; |
---|
124 | case INSN_STR: |
---|
125 | printk("\n\nINSN_STR\n"); |
---|
126 | break; |
---|
127 | case INSN_STRB: |
---|
128 | printk("\n\nINSN_STRB\n"); |
---|
129 | break; |
---|
130 | case INSN_LDM1: |
---|
131 | printk("\n\nINSN_LDM1\n"); |
---|
132 | break; |
---|
133 | case INSN_LDM23: |
---|
134 | printk("\n\nINSN_LDM23\n"); |
---|
135 | break; |
---|
136 | case INSN_LDR: |
---|
137 | printk("\n\nINSN_LDR\n"); |
---|
138 | break; |
---|
139 | case INSN_LDRB: |
---|
140 | printk("\n\nINSN_LDRB\n"); |
---|
141 | break; |
---|
142 | default: |
---|
143 | printk("\n\nUnrecognized instruction\n"); |
---|
144 | break; |
---|
145 | } |
---|
146 | |
---|
147 | printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n", |
---|
148 | ctx->register_lr - 8, insn, spsr); |
---|
149 | |
---|
150 | _print_full_context(spsr); |
---|
151 | |
---|
152 | /* disable interrupts, wait forever */ |
---|
153 | rtems_interrupt_disable(level); |
---|
154 | while(1) { |
---|
155 | continue; |
---|
156 | } |
---|
157 | return; |
---|
158 | } |
---|
159 | |
---|