1 | /* |
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2 | * ARM CPU Dependent Source |
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3 | * |
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4 | * If you want a small footprint RTEMS, pls use simple_abort.c |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 2007 Ray Xu. |
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9 | * mailto: Rayx at gmail dot com |
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10 | * |
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11 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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12 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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13 | * |
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14 | * Copyright (c) 2002 Advent Networks, Inc |
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15 | * Jay Monkman <jmonkman@adventnetworks.com> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | * |
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21 | */ |
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22 | |
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23 | #include <rtems/system.h> |
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24 | #include <rtems.h> |
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25 | #include <rtems/bspIo.h> |
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26 | #include "abort.h" |
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27 | |
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28 | uint32_t g_data_abort_cnt = 0; |
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29 | /*this is a big overhead for MCU only got 16K RAM*/ |
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30 | uint32_t g_data_abort_insn_list[1024]; |
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31 | |
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32 | |
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33 | char *_print_full_context_mode2txt[0x20]={ |
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34 | [0x0]="user", /* User */ |
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35 | [0x1]="fiq", /* FIQ - Fast Interrupt Request */ |
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36 | [0x2]="irq", /* IRQ - Interrupt Request */ |
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37 | [0x3]="super", /* Supervisor */ |
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38 | [0x7]="abort", /* Abort */ |
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39 | [0xb]="undef", /* Undefined */ |
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40 | [0xf]="system" /* System */ |
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41 | }; |
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42 | |
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43 | void _print_full_context(uint32_t spsr) |
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44 | { |
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45 | char *mode; |
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46 | uint32_t prev_sp,prev_lr,cpsr,arm_switch_reg; |
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47 | int i; |
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48 | |
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49 | printk("active thread thread 0x%08x\n", rtems_task_self()); |
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50 | |
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51 | mode=_print_full_context_mode2txt[spsr&0x1f]; |
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52 | if(!mode) mode="unknown"; |
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53 | |
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54 | __asm__ volatile (ARM_SWITCH_TO_ARM |
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55 | " MRS %[cpsr], cpsr \n" |
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56 | " ORR %[arm_switch_reg], %[spsr], #0xc0 \n" |
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57 | " MSR cpsr_c, %[arm_switch_reg] \n" |
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58 | " MOV %[prev_sp], sp \n" |
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59 | " MOV %[prev_lr], lr \n" |
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60 | " MSR cpsr_c, %[cpsr] \n" |
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61 | ARM_SWITCH_BACK |
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62 | : [arm_switch_reg] "=&r" (arm_switch_reg), [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr), |
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63 | [cpsr] "=&r" (cpsr) |
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64 | : [spsr] "r" (spsr) |
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65 | : "cc"); |
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66 | |
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67 | printk("Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n", |
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68 | prev_sp, prev_lr, cpsr); |
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69 | |
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70 | for(i=0;i<48;){ |
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71 | printk(" 0x%08x",((uint32_t*)prev_sp)[i++]); |
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72 | if((i%6) == 0) |
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73 | printk("\n"); |
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74 | } |
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75 | |
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76 | } |
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77 | |
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78 | |
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79 | /* This function is supposed to figure out what caused the |
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80 | * data abort, do that, then return. |
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81 | * |
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82 | * All unhandled instructions cause the system to hang. |
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83 | */ |
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84 | |
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85 | void do_data_abort( |
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86 | uint32_t insn, |
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87 | uint32_t spsr, |
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88 | Context_Control *ctx |
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89 | ) |
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90 | { |
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91 | /* Clarify, which type is correct, CPU_Exception_frame or Context_Control */ |
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92 | uint8_t decode; |
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93 | uint8_t insn_type; |
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94 | rtems_interrupt_level level; |
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95 | |
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96 | g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8; |
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97 | g_data_abort_cnt++; |
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98 | |
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99 | decode = ((insn >> 20) & 0xff); |
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100 | |
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101 | insn_type = decode & INSN_MASK; |
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102 | switch(insn_type) { |
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103 | case INSN_STM1: |
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104 | printk("\n\nINSN_STM1\n"); |
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105 | break; |
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106 | case INSN_STM2: |
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107 | printk("\n\nINSN_STM2\n"); |
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108 | break; |
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109 | case INSN_STR: |
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110 | printk("\n\nINSN_STR\n"); |
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111 | break; |
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112 | case INSN_STRB: |
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113 | printk("\n\nINSN_STRB\n"); |
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114 | break; |
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115 | case INSN_LDM1: |
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116 | printk("\n\nINSN_LDM1\n"); |
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117 | break; |
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118 | case INSN_LDM23: |
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119 | printk("\n\nINSN_LDM23\n"); |
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120 | break; |
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121 | case INSN_LDR: |
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122 | printk("\n\nINSN_LDR\n"); |
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123 | break; |
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124 | case INSN_LDRB: |
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125 | printk("\n\nINSN_LDRB\n"); |
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126 | break; |
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127 | default: |
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128 | printk("\n\nUnrecognized instruction\n"); |
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129 | break; |
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130 | } |
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131 | |
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132 | printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n", |
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133 | ctx->register_lr - 8, insn, spsr); |
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134 | |
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135 | _print_full_context(spsr); |
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136 | |
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137 | /* disable interrupts, wait forever */ |
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138 | rtems_interrupt_disable(level); |
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139 | (void) level; /* avoid set but unused warning */ |
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140 | |
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141 | while(1) { |
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142 | continue; |
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143 | } |
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144 | } |
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145 | |
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