source: rtems/c/src/lib/libbsp/arm/rtl22xx/start/start.S @ e890774

4.104.114.84.9
Last change on this file since e890774 was e890774, checked in by Joel Sherrill <joel.sherrill@…>, on May 1, 2007 at 7:15:38 PM

2007-05-01 Ray Xu <xr@…>

  • README, times, console/lpc22xx_uart.h, console/uart.c, include/bsp.h, start/start.S, startup/bspstart.c, startup/exit.c, startup/linkcmds: Update BSP to address changes between 4.7 and CVS head as well as to address comments from Ralf and Joel.
  • Property mode set to 100644
File size: 5.2 KB
Line 
1/*
2 * Philips LPC22XX/LPC21xx Startup code
3 *
4 * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com>
5 * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com>
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *
12 *  $Id$
13*/
14
15/* Some standard definitions...*/
16
17/* Some standard definitions...*/
18.equ PSR_MODE_USR,       0x10
19.equ PSR_MODE_FIQ,       0x11
20.equ PSR_MODE_IRQ,       0x12
21.equ PSR_MODE_SVC,       0x13
22.equ PSR_MODE_ABT,       0x17
23.equ PSR_MODE_UNDEF,     0x1B
24.equ PSR_MODE_SYS,       0x1F
25
26.equ PSR_I,              0x80
27.equ PSR_F,              0x40
28.equ PSR_T,              0x20
29
30.text
31.globl  _start
32_start:
33        /*
34         * Since I don't plan to return to the bootloader,
35         * I don't have to save the registers.
36         *
37         * I'll just set the CPSR for SVC mode, interrupts
38         * off, and ARM instructions.
39         */
40        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
41        msr     cpsr, r0
42
43        /* zero the bss */
44        ldr     r1, =_bss_end_
45        ldr     r0, =_bss_start_
46
47_bss_init:       
48        mov     r2, #0
49        cmp     r0, r1
50        strlot  r2, [r0], #4
51        blo     _bss_init        /* loop while r0 < r1 */
52       
53        /* --- Initialize stack pointer registers */
54        /* Enter IRQ mode and set up the IRQ stack pointer */
55        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
56        msr     cpsr, r0
57        ldr     r1, =_irq_stack_size
58        ldr     sp, =_irq_stack
59        add     sp, sp, r1
60
61        /* Enter FIQ mode and set up the FIQ stack pointer */
62        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
63        msr     cpsr, r0
64        ldr     r1, =_fiq_stack_size
65        ldr     sp, =_fiq_stack
66        add     sp, sp, r1
67
68        /* Enter ABT mode and set up the ABT stack pointer */
69        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
70        msr     cpsr, r0
71        ldr     r1, =_abt_stack_size
72        ldr     sp, =_abt_stack
73        add     sp, sp, r1
74       
75        /* Set up the SVC stack pointer last and stay in SVC mode */
76        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
77        msr     cpsr, r0
78        ldr     r1, =_svc_stack_size
79        ldr     sp, =_svc_stack
80        add     sp, sp, r1
81        sub     sp, sp, #0x64   
82             
83
84        /*
85         * Initialize the exception vectors. This includes the
86         * exceptions vectors (0x00000000-0x0000001c), and the
87         * pointers to the exception handlers (0x00000020-0x0000003c).
88         */
89        mov     r0, #0
90        adr     r1, vector_block
91        ldmia   r1!, {r2-r9}
92        stmia   r0!, {r2-r9}
93        ldmia   r1!, {r2-r9}
94        stmia   r0!, {r2-r9}
95
96        /* Now we are prepared to start the BSP's C code */
97        bl      boot_card
98
99        /*
100         * Theoretically, we could return to what started us up,
101         * but we'd have to have saved the registers and stacks.
102         * Instead, we'll just reset.
103         */
104        bl      bsp_reset
105
106        /* We shouldn't get here. If we do, hang */
107_hang:  b       _hang
108
109
110/*******************************************************
111 standard exception vectors table
112 *** Must be located at address 0
113********************************************************/
114
115vector_block:
116        LDR     PC, Reset_Addr
117        LDR     PC, Undefined_Addr
118        LDR     PC, SWI_Addr
119        LDR     PC, Prefetch_Addr
120        LDR     PC, Abort_Addr
121        NOP
122        LDR     PC, IRQ_Addr
123        LDR     PC, FIQ_Addr
124
125        .globl Reset_Addr
126Reset_Addr:     .long   _start
127Undefined_Addr: .long   Undefined_Handler
128SWI_Addr:       .long   SWI_Handler
129Prefetch_Addr:  .long   Prefetch_Handler
130Abort_Addr:     .long   Abort_Handler
131                .long   0
132IRQ_Addr:       .long   IRQ_Handler
133FIQ_Addr:       .long   FIQ_Handler
134
135/* The following handlers do not do anything useful */
136        .globl Undefined_Handler
137Undefined_Handler:
138        B       Undefined_Handler
139        .globl SWI_Handler
140SWI_Handler:
141        B       SWI_Handler
142        .globl Prefetch_Handler
143Prefetch_Handler:
144        B       Prefetch_Handler
145        .globl Abort_Handler
146Abort_Handler:
147        B       Abort_Handler
148        .globl IRQ_Handler
149IRQ_Handler:
150        B       IRQ_Handler
151        .globl FIQ_Handler
152FIQ_Handler:
153        B       FIQ_Handler
154
155
156
157       
158/*
159 * This is the exception vector table and the pointers to
160 * the functions that handle the exceptions. It's a total
161 * of 16 words (64 bytes)
162 */
163
164 /*******************************************************
165
166vector_block:   
167        ldr     pc, Reset_Handler
168        ldr     pc, Undefined_Handler
169        ldr     pc, SWI_Handler
170        ldr     pc, Prefetch_Handler
171        ldr     pc, Abort_Handler
172        nop
173        ldr     pc, IRQ_Handler
174        ldr     pc, FIQ_Handler
175
176Reset_Handler:          b       bsp_reset
177Undefined_Handler:      b       Undefined_Handler
178SWI_Handler:            b       SWI_Handler
179Prefetch_Handler:       b       Prefetch_Handler
180Abort_Handler:          b       Abort_Handler
181                        nop
182IRQ_Handler:            b       IRQ_Handler
183FIQ_Handler:            b       FIQ_Handler
184
185.globl Reset_Handler
186.globl Undefined_Handler
187.globl SWI_Handler
188.globl Prefetch_Handler
189.globl Abort_Handler
190.globl IRQ_Handler
191.globl FIQ_Handler
192 */
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