source: rtems/c/src/lib/libbsp/arm/rtl22xx/start/start.S @ 2433a8ab

5
Last change on this file since 2433a8ab was 2433a8ab, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 7, 2017 at 1:32:42 PM

arm: Remove legacy execption support

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 * Philips LPC22XX/LPC21xx Startup code
3 *
4 * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com>
5 * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com>
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9*/
10
11#include <bsp/linker-symbols.h>
12
13/* Some standard definitions...*/
14.equ PSR_MODE_USR,       0x10
15.equ PSR_MODE_FIQ,       0x11
16.equ PSR_MODE_IRQ,       0x12
17.equ PSR_MODE_SVC,       0x13
18.equ PSR_MODE_ABT,       0x17
19.equ PSR_MODE_UNDEF,     0x1B
20.equ PSR_MODE_SYS,       0x1F
21
22.equ PSR_I,              0x80
23.equ PSR_F,              0x40
24.equ PSR_T,              0x20
25
26.text
27.code   32
28.globl  _start
29_start:
30        /*
31         * Since I don't plan to return to the bootloader,
32         * I don't have to save the registers.
33         *
34         * I'll just set the CPSR for SVC mode, interrupts
35         * off, and ARM instructions.
36         */
37
38        /* --- Initialize stack pointer registers */
39        /* Enter IRQ mode and set up the IRQ stack pointer */
40        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
41        bic     r0, r0, #PSR_T
42        msr     cpsr, r0
43        ldr     r1, =bsp_stack_irq_size
44        ldr     sp, =bsp_stack_irq_begin
45        add     sp, sp, r1
46
47        /* Enter FIQ mode and set up the FIQ stack pointer */
48        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
49        bic     r0, r0, #PSR_T
50        msr     cpsr, r0
51        ldr     r1, =bsp_stack_fiq_size
52        ldr     sp, =bsp_stack_fiq_begin
53        add     sp, sp, r1
54
55        /* Enter ABT mode and set up the ABT stack pointer */
56        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
57        bic     r0, r0, #PSR_T
58        msr     cpsr, r0
59        bic     r0, r0, #PSR_T
60        ldr     r1, =bsp_stack_abt_size
61        ldr     sp, =bsp_stack_abt_begin
62        add     sp, sp, r1
63
64        /* Set up the SVC stack pointer last and stay in SVC mode */
65        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
66        bic     r0, r0, #PSR_T
67        msr     cpsr, r0
68        ldr     r1, =bsp_stack_svc_size
69        ldr     sp, =bsp_stack_svc_begin
70        add     sp, sp, r1
71        sub     sp, sp, #0x64
72
73        /*
74         * Initialize the exception vectors. This includes the
75         * exceptions vectors (0x00000000-0x0000001c), and the
76         * pointers to the exception handlers (0x00000020-0x0000003c).
77         */
78        mov     r0, #0
79        adr     r1, vector_block
80        ldmia   r1!, {r2-r9}
81        stmia   r0!, {r2-r9}
82
83        ldmia   r1!, {r2-r9}
84        stmia   r0!, {r2-r9}
85
86
87        /* zero the bss */
88        ldr     r1, =bsp_section_bss_end
89        ldr     r0, =bsp_section_bss_begin
90
91_bss_init:
92        mov     r2, #0
93        cmp     r0, r1
94        strlot  r2, [r0], #4
95        blo     _bss_init        /* loop while r0 < r1 */
96
97
98        /* Now we are prepared to start the BSP's C code */
99        mov     r0, #0
100#ifdef __thumb__
101        ldr     r3, =boot_card
102        bx      r3
103#else
104        bl      boot_card
105
106
107        /*
108         * Theoretically, we could return to what started us up,
109         * but we'd have to have saved the registers and stacks.
110         * Instead, we'll just reset.
111         */
112        bl      bsp_reset
113#endif
114        .code   32
115
116        /* We shouldn't get here. If we do, hang */
117_hang:  b       _hang
118
119
120/*******************************************************
121 standard exception vectors table
122 *** Must be located at address 0
123********************************************************/
124
125vector_block:
126        ldr    pc, handler_addr_reset
127        ldr    pc, handler_addr_undef
128        ldr    pc, handler_addr_swi
129        ldr    pc, handler_addr_prefetch
130        ldr    pc, handler_addr_abort
131        nop
132        ldr    pc, handler_addr_irq
133        ldr    pc, handler_addr_fiq
134
135handler_addr_reset:
136        .word  _start
137
138handler_addr_undef:
139        .word  _ARMV4_Exception_undef_default
140
141handler_addr_swi:
142        .word  _ARMV4_Exception_swi_default
143
144handler_addr_prefetch:
145        .word  _ARMV4_Exception_pref_abort_default
146
147handler_addr_abort:
148        .word  _ARMV4_Exception_data_abort_default
149
150handler_addr_reserved:
151        .word  _ARMV4_Exception_reserved_default
152
153handler_addr_irq:
154        .word  _ARMV4_Exception_interrupt
155
156handler_addr_fiq:
157        .word  _ARMV4_Exception_fiq_default
Note: See TracBrowser for help on using the repository browser.