source: rtems/c/src/lib/libbsp/arm/rtl22xx/start/start.S @ 13ce840

4.104.114.84.9
Last change on this file since 13ce840 was 13ce840, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 25, 2007 at 1:18:54 PM

Add missing newline.

  • Property mode set to 100644
File size: 5.2 KB
Line 
1/*
2 * Philips LPC22XX Startup code
3 *
4 * Copyright (c) 2005 Ray xu
5 *
6 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
7 *
8 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *
16 *  $Id$
17*/
18
19/* Some standard definitions...*/
20
21/* Some standard definitions...*/
22.equ PSR_MODE_USR,       0x10
23.equ PSR_MODE_FIQ,       0x11
24.equ PSR_MODE_IRQ,       0x12
25.equ PSR_MODE_SVC,       0x13
26.equ PSR_MODE_ABT,       0x17
27.equ PSR_MODE_UNDEF,     0x1B
28.equ PSR_MODE_SYS,       0x1F
29
30.equ PSR_I,              0x80
31.equ PSR_F,              0x40
32.equ PSR_T,              0x20
33
34.text
35.globl  _start
36_start:
37        /*
38         * Since I don't plan to return to the bootloader,
39         * I don't have to save the registers.
40         *
41         * I'll just set the CPSR for SVC mode, interrupts
42         * off, and ARM instructions.
43         */
44        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
45        msr     cpsr, r0
46
47        /* zero the bss */
48        ldr     r1, =_bss_end_
49        ldr     r0, =_bss_start_
50
51_bss_init:       
52        mov     r2, #0
53        cmp     r0, r1
54        strlot  r2, [r0], #4
55        blo     _bss_init        /* loop while r0 < r1 */
56       
57        /* --- Initialize stack pointer registers */
58        /* Enter IRQ mode and set up the IRQ stack pointer */
59        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
60        msr     cpsr, r0
61        ldr     r1, =_irq_stack_size
62        ldr     sp, =_irq_stack
63        add     sp, sp, r1
64
65        /* Enter FIQ mode and set up the FIQ stack pointer */
66        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
67        msr     cpsr, r0
68        ldr     r1, =_fiq_stack_size
69        ldr     sp, =_fiq_stack
70        add     sp, sp, r1
71
72        /* Enter ABT mode and set up the ABT stack pointer */
73        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
74        msr     cpsr, r0
75        ldr     r1, =_abt_stack_size
76        ldr     sp, =_abt_stack
77        add     sp, sp, r1
78       
79        /* Set up the SVC stack pointer last and stay in SVC mode */
80        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
81        msr     cpsr, r0
82        ldr     r1, =_svc_stack_size
83        ldr     sp, =_svc_stack
84        add     sp, sp, r1
85        sub     sp, sp, #0x64   
86             
87
88        /*
89         * Initialize the exception vectors. This includes the
90         * exceptions vectors (0x00000000-0x0000001c), and the
91         * pointers to the exception handlers (0x00000020-0x0000003c).
92         */
93        mov     r0, #0
94        adr     r1, vector_block
95        ldmia   r1!, {r2-r9}
96        stmia   r0!, {r2-r9}
97        ldmia   r1!, {r2-r9}
98        stmia   r0!, {r2-r9}
99
100        /* Now we are prepared to start the BSP's C code */
101        bl      boot_card
102
103        /*
104         * Theoretically, we could return to what started us up,
105         * but we'd have to have saved the registers and stacks.
106         * Instead, we'll just reset.
107         */
108        bl      bsp_reset
109
110        /* We shouldn't get here. If we do, hang */
111_hang:  b       _hang
112
113
114/*******************************************************
115 standard exception vectors table
116 *** Must be located at address 0
117********************************************************/
118
119vector_block:
120        LDR     PC, Reset_Addr
121        LDR     PC, Undefined_Addr
122        LDR     PC, SWI_Addr
123        LDR     PC, Prefetch_Addr
124        LDR     PC, Abort_Addr
125        NOP
126        LDR     PC, IRQ_Addr
127        LDR     PC, FIQ_Addr
128
129        .globl Reset_Addr
130Reset_Addr:     .long   _start
131Undefined_Addr: .long   Undefined_Handler
132SWI_Addr:       .long   SWI_Handler
133Prefetch_Addr:  .long   Prefetch_Handler
134Abort_Addr:     .long   Abort_Handler
135                .long   0
136IRQ_Addr:       .long   IRQ_Handler
137FIQ_Addr:       .long   FIQ_Handler
138
139/* The following handlers do not do anything useful */
140        .globl Undefined_Handler
141Undefined_Handler:
142        B       Undefined_Handler
143        .globl SWI_Handler
144SWI_Handler:
145        B       SWI_Handler
146        .globl Prefetch_Handler
147Prefetch_Handler:
148        B       Prefetch_Handler
149        .globl Abort_Handler
150Abort_Handler:
151        B       Abort_Handler
152        .globl IRQ_Handler
153IRQ_Handler:
154        B       IRQ_Handler
155        .globl FIQ_Handler
156FIQ_Handler:
157        B       FIQ_Handler
158
159
160
161       
162/*
163 * This is the exception vector table and the pointers to
164 * the functions that handle the exceptions. It's a total
165 * of 16 words (64 bytes)
166 */
167
168 /*******************************************************
169
170vector_block:   
171        ldr     pc, Reset_Handler
172        ldr     pc, Undefined_Handler
173        ldr     pc, SWI_Handler
174        ldr     pc, Prefetch_Handler
175        ldr     pc, Abort_Handler
176        nop
177        ldr     pc, IRQ_Handler
178        ldr     pc, FIQ_Handler
179
180Reset_Handler:          b       bsp_reset
181Undefined_Handler:      b       Undefined_Handler
182SWI_Handler:            b       SWI_Handler
183Prefetch_Handler:       b       Prefetch_Handler
184Abort_Handler:          b       Abort_Handler
185                        nop
186IRQ_Handler:            b       IRQ_Handler
187FIQ_Handler:            b       FIQ_Handler
188
189.globl Reset_Handler
190.globl Undefined_Handler
191.globl SWI_Handler
192.globl Prefetch_Handler
193.globl Abort_Handler
194.globl IRQ_Handler
195.globl FIQ_Handler
196 */
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