1 | /* |
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2 | * Philips LPC22XX/LPC21xx Startup code |
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3 | * |
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4 | * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com> |
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5 | * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com> |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <bsp/linker-symbols.h> |
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12 | |
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13 | /* Some standard definitions...*/ |
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14 | .equ PSR_MODE_USR, 0x10 |
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15 | .equ PSR_MODE_FIQ, 0x11 |
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16 | .equ PSR_MODE_IRQ, 0x12 |
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17 | .equ PSR_MODE_SVC, 0x13 |
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18 | .equ PSR_MODE_ABT, 0x17 |
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19 | .equ PSR_MODE_UNDEF, 0x1B |
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20 | .equ PSR_MODE_SYS, 0x1F |
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21 | |
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22 | .equ PSR_I, 0x80 |
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23 | .equ PSR_F, 0x40 |
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24 | .equ PSR_T, 0x20 |
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25 | |
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26 | .text |
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27 | .code 32 |
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28 | .globl _start |
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29 | _start: |
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30 | /* |
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31 | * Since I don't plan to return to the bootloader, |
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32 | * I don't have to save the registers. |
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33 | * |
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34 | * I'll just set the CPSR for SVC mode, interrupts |
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35 | * off, and ARM instructions. |
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36 | */ |
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37 | |
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38 | /* --- Initialize stack pointer registers */ |
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39 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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40 | mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ |
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41 | bic r0, r0, #PSR_T |
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42 | msr cpsr, r0 |
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43 | ldr r1, =bsp_stack_irq_size |
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44 | ldr sp, =bsp_stack_irq_begin |
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45 | add sp, sp, r1 |
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46 | |
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47 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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48 | mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ |
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49 | bic r0, r0, #PSR_T |
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50 | msr cpsr, r0 |
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51 | ldr r1, =bsp_stack_fiq_size |
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52 | ldr sp, =bsp_stack_fiq_begin |
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53 | add sp, sp, r1 |
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54 | |
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55 | /* Enter ABT mode and set up the ABT stack pointer */ |
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56 | mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ |
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57 | bic r0, r0, #PSR_T |
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58 | msr cpsr, r0 |
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59 | bic r0, r0, #PSR_T |
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60 | ldr r1, =bsp_stack_abt_size |
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61 | ldr sp, =bsp_stack_abt_begin |
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62 | add sp, sp, r1 |
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63 | |
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64 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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65 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ |
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66 | bic r0, r0, #PSR_T |
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67 | msr cpsr, r0 |
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68 | ldr r1, =bsp_stack_svc_size |
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69 | ldr sp, =bsp_stack_svc_begin |
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70 | add sp, sp, r1 |
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71 | sub sp, sp, #0x64 |
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72 | |
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73 | /* |
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74 | * Initialize the exception vectors. This includes the |
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75 | * exceptions vectors (0x00000000-0x0000001c), and the |
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76 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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77 | */ |
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78 | mov r0, #0 |
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79 | adr r1, vector_block |
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80 | ldmia r1!, {r2-r9} |
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81 | stmia r0!, {r2-r9} |
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82 | |
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83 | ldmia r1!, {r2-r9} |
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84 | stmia r0!, {r2-r9} |
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85 | |
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86 | |
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87 | /* zero the bss */ |
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88 | ldr r1, =bsp_section_bss_end |
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89 | ldr r0, =bsp_section_bss_begin |
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90 | |
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91 | _bss_init: |
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92 | mov r2, #0 |
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93 | cmp r0, r1 |
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94 | strlot r2, [r0], #4 |
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95 | blo _bss_init /* loop while r0 < r1 */ |
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96 | |
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97 | |
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98 | /* Now we are prepared to start the BSP's C code */ |
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99 | mov r0, #0 |
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100 | #ifdef __thumb__ |
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101 | ldr r3, =boot_card |
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102 | bx r3 |
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103 | #else |
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104 | bl boot_card |
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105 | |
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106 | |
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107 | /* |
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108 | * Theoretically, we could return to what started us up, |
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109 | * but we'd have to have saved the registers and stacks. |
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110 | * Instead, we'll just reset. |
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111 | */ |
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112 | bl bsp_reset |
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113 | #endif |
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114 | .code 32 |
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115 | |
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116 | /* We shouldn't get here. If we do, hang */ |
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117 | _hang: b _hang |
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118 | |
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119 | |
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120 | /******************************************************* |
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121 | standard exception vectors table |
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122 | *** Must be located at address 0 |
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123 | ********************************************************/ |
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124 | |
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125 | vector_block: |
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126 | LDR PC, Reset_Addr |
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127 | LDR PC, Undefined_Addr |
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128 | LDR PC, SWI_Addr |
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129 | LDR PC, Prefetch_Addr |
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130 | LDR PC, Abort_Addr |
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131 | NOP |
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132 | LDR PC, IRQ_Addr |
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133 | LDR PC, FIQ_Addr |
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134 | |
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135 | .globl Reset_Addr |
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136 | Reset_Addr: .long _start |
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137 | Undefined_Addr: .long Undefined_Handler |
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138 | SWI_Addr: .long SWI_Handler |
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139 | Prefetch_Addr: .long Prefetch_Handler |
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140 | Abort_Addr: .long Abort_Handler |
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141 | .long 0 |
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142 | IRQ_Addr: .long IRQ_Handler |
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143 | FIQ_Addr: .long FIQ_Handler |
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144 | |
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145 | /* The following handlers do not do anything useful */ |
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146 | .globl Undefined_Handler |
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147 | Undefined_Handler: |
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148 | B Undefined_Handler |
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149 | .globl SWI_Handler |
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150 | SWI_Handler: |
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151 | B SWI_Handler |
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152 | .globl Prefetch_Handler |
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153 | Prefetch_Handler: |
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154 | B Prefetch_Handler |
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155 | .globl Abort_Handler |
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156 | Abort_Handler: |
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157 | B Abort_Handler |
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158 | .globl IRQ_Handler |
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159 | IRQ_Handler: |
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160 | B IRQ_Handler |
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161 | .globl FIQ_Handler |
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162 | FIQ_Handler: |
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163 | B FIQ_Handler |
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164 | |
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165 | |
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166 | |
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167 | |
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168 | /* |
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169 | * This is the exception vector table and the pointers to |
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170 | * the functions that handle the exceptions. It's a total |
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171 | * of 16 words (64 bytes) |
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172 | */ |
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173 | |
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174 | /******************************************************* |
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175 | |
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176 | vector_block: |
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177 | ldr pc, Reset_Handler |
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178 | ldr pc, Undefined_Handler |
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179 | ldr pc, SWI_Handler |
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180 | ldr pc, Prefetch_Handler |
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181 | ldr pc, Abort_Handler |
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182 | nop |
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183 | ldr pc, IRQ_Handler |
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184 | ldr pc, FIQ_Handler |
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185 | |
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186 | Reset_Handler: b bsp_reset |
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187 | Undefined_Handler: b Undefined_Handler |
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188 | SWI_Handler: b SWI_Handler |
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189 | Prefetch_Handler: b Prefetch_Handler |
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190 | Abort_Handler: b Abort_Handler |
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191 | nop |
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192 | IRQ_Handler: b IRQ_Handler |
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193 | FIQ_Handler: b FIQ_Handler |
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194 | |
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195 | .globl Reset_Handler |
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196 | .globl Undefined_Handler |
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197 | .globl SWI_Handler |
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198 | .globl Prefetch_Handler |
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199 | .globl Abort_Handler |
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200 | .globl IRQ_Handler |
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201 | .globl FIQ_Handler |
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202 | */ |
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