[8a3c70b] | 1 | /* |
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[e890774] | 2 | * Philips LPC22XX/LPC21xx Startup code |
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[8a3c70b] | 3 | * |
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[e890774] | 4 | * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com> |
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| 5 | * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com> |
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[8a3c70b] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | /* Some standard definitions...*/ |
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| 16 | |
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| 17 | /* Some standard definitions...*/ |
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| 18 | .equ PSR_MODE_USR, 0x10 |
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| 19 | .equ PSR_MODE_FIQ, 0x11 |
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| 20 | .equ PSR_MODE_IRQ, 0x12 |
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| 21 | .equ PSR_MODE_SVC, 0x13 |
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| 22 | .equ PSR_MODE_ABT, 0x17 |
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| 23 | .equ PSR_MODE_UNDEF, 0x1B |
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| 24 | .equ PSR_MODE_SYS, 0x1F |
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| 25 | |
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| 26 | .equ PSR_I, 0x80 |
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| 27 | .equ PSR_F, 0x40 |
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| 28 | .equ PSR_T, 0x20 |
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| 29 | |
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| 30 | .text |
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| 31 | .globl _start |
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| 32 | _start: |
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| 33 | /* |
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| 34 | * Since I don't plan to return to the bootloader, |
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| 35 | * I don't have to save the registers. |
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| 36 | * |
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| 37 | * I'll just set the CPSR for SVC mode, interrupts |
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| 38 | * off, and ARM instructions. |
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| 39 | */ |
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| 40 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) |
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| 41 | msr cpsr, r0 |
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| 42 | |
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| 43 | /* zero the bss */ |
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| 44 | ldr r1, =_bss_end_ |
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| 45 | ldr r0, =_bss_start_ |
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| 46 | |
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| 47 | _bss_init: |
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| 48 | mov r2, #0 |
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| 49 | cmp r0, r1 |
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| 50 | strlot r2, [r0], #4 |
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| 51 | blo _bss_init /* loop while r0 < r1 */ |
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| 52 | |
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| 53 | /* --- Initialize stack pointer registers */ |
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| 54 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 55 | mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ |
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| 56 | msr cpsr, r0 |
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| 57 | ldr r1, =_irq_stack_size |
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| 58 | ldr sp, =_irq_stack |
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| 59 | add sp, sp, r1 |
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| 60 | |
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| 61 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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| 62 | mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ |
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| 63 | msr cpsr, r0 |
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| 64 | ldr r1, =_fiq_stack_size |
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| 65 | ldr sp, =_fiq_stack |
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| 66 | add sp, sp, r1 |
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| 67 | |
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| 68 | /* Enter ABT mode and set up the ABT stack pointer */ |
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| 69 | mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ |
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| 70 | msr cpsr, r0 |
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| 71 | ldr r1, =_abt_stack_size |
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| 72 | ldr sp, =_abt_stack |
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| 73 | add sp, sp, r1 |
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| 74 | |
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| 75 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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| 76 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ |
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| 77 | msr cpsr, r0 |
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| 78 | ldr r1, =_svc_stack_size |
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| 79 | ldr sp, =_svc_stack |
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| 80 | add sp, sp, r1 |
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| 81 | sub sp, sp, #0x64 |
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| 82 | |
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| 83 | |
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| 84 | /* |
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| 85 | * Initialize the exception vectors. This includes the |
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| 86 | * exceptions vectors (0x00000000-0x0000001c), and the |
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| 87 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 88 | */ |
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| 89 | mov r0, #0 |
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| 90 | adr r1, vector_block |
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| 91 | ldmia r1!, {r2-r9} |
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| 92 | stmia r0!, {r2-r9} |
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| 93 | ldmia r1!, {r2-r9} |
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| 94 | stmia r0!, {r2-r9} |
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| 95 | |
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| 96 | /* Now we are prepared to start the BSP's C code */ |
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| 97 | bl boot_card |
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| 98 | |
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| 99 | /* |
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| 100 | * Theoretically, we could return to what started us up, |
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| 101 | * but we'd have to have saved the registers and stacks. |
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| 102 | * Instead, we'll just reset. |
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| 103 | */ |
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| 104 | bl bsp_reset |
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| 105 | |
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| 106 | /* We shouldn't get here. If we do, hang */ |
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| 107 | _hang: b _hang |
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| 108 | |
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| 109 | |
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| 110 | /******************************************************* |
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| 111 | standard exception vectors table |
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| 112 | *** Must be located at address 0 |
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| 113 | ********************************************************/ |
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| 114 | |
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| 115 | vector_block: |
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| 116 | LDR PC, Reset_Addr |
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| 117 | LDR PC, Undefined_Addr |
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| 118 | LDR PC, SWI_Addr |
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| 119 | LDR PC, Prefetch_Addr |
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| 120 | LDR PC, Abort_Addr |
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| 121 | NOP |
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| 122 | LDR PC, IRQ_Addr |
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| 123 | LDR PC, FIQ_Addr |
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| 124 | |
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| 125 | .globl Reset_Addr |
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| 126 | Reset_Addr: .long _start |
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| 127 | Undefined_Addr: .long Undefined_Handler |
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| 128 | SWI_Addr: .long SWI_Handler |
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| 129 | Prefetch_Addr: .long Prefetch_Handler |
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| 130 | Abort_Addr: .long Abort_Handler |
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| 131 | .long 0 |
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| 132 | IRQ_Addr: .long IRQ_Handler |
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| 133 | FIQ_Addr: .long FIQ_Handler |
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| 134 | |
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| 135 | /* The following handlers do not do anything useful */ |
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| 136 | .globl Undefined_Handler |
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| 137 | Undefined_Handler: |
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| 138 | B Undefined_Handler |
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| 139 | .globl SWI_Handler |
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| 140 | SWI_Handler: |
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| 141 | B SWI_Handler |
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| 142 | .globl Prefetch_Handler |
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| 143 | Prefetch_Handler: |
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| 144 | B Prefetch_Handler |
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| 145 | .globl Abort_Handler |
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| 146 | Abort_Handler: |
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| 147 | B Abort_Handler |
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| 148 | .globl IRQ_Handler |
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| 149 | IRQ_Handler: |
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| 150 | B IRQ_Handler |
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| 151 | .globl FIQ_Handler |
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| 152 | FIQ_Handler: |
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| 153 | B FIQ_Handler |
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| 154 | |
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| 155 | |
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| 156 | |
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| 157 | |
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| 158 | /* |
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| 159 | * This is the exception vector table and the pointers to |
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| 160 | * the functions that handle the exceptions. It's a total |
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| 161 | * of 16 words (64 bytes) |
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| 162 | */ |
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| 163 | |
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| 164 | /******************************************************* |
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| 165 | |
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| 166 | vector_block: |
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| 167 | ldr pc, Reset_Handler |
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| 168 | ldr pc, Undefined_Handler |
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| 169 | ldr pc, SWI_Handler |
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| 170 | ldr pc, Prefetch_Handler |
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| 171 | ldr pc, Abort_Handler |
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| 172 | nop |
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| 173 | ldr pc, IRQ_Handler |
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| 174 | ldr pc, FIQ_Handler |
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| 175 | |
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| 176 | Reset_Handler: b bsp_reset |
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| 177 | Undefined_Handler: b Undefined_Handler |
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| 178 | SWI_Handler: b SWI_Handler |
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| 179 | Prefetch_Handler: b Prefetch_Handler |
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| 180 | Abort_Handler: b Abort_Handler |
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| 181 | nop |
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| 182 | IRQ_Handler: b IRQ_Handler |
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| 183 | FIQ_Handler: b FIQ_Handler |
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| 184 | |
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| 185 | .globl Reset_Handler |
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| 186 | .globl Undefined_Handler |
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| 187 | .globl SWI_Handler |
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| 188 | .globl Prefetch_Handler |
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| 189 | .globl Abort_Handler |
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| 190 | .globl IRQ_Handler |
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| 191 | .globl FIQ_Handler |
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[13ce840] | 192 | */ |
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