1 | /* |
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2 | * Interrupt handler Header file |
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3 | * |
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4 | * Copyright (c) 2010 embedded brains GmbH. |
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5 | * |
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6 | * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.org/license/LICENSE. |
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11 | */ |
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12 | |
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13 | #ifndef __IRQ_H__ |
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14 | #define __IRQ_H__ |
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15 | |
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16 | #ifndef __asm__ |
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17 | |
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18 | #include <rtems.h> |
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19 | #include <rtems/irq.h> |
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20 | #include <rtems/irq-extension.h> |
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21 | |
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22 | #endif /* __asm__ */ |
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23 | |
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24 | /* possible interrupt sources on the LPC22xx */ |
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25 | #define LPC22xx_INTERRUPT_WDINT 0 /* Watchdog int. 0 */ |
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26 | #define LPC22xx_INTERRUPT_RSV0 1 /* Reserved int. 1 */ |
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27 | #define LPC22xx_INTERRUPT_DBGRX 2 /* Embedded ICE DbgCommRx receive */ |
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28 | #define LPC22xx_INTERRUPT_DBGTX 3 /* Embedded ICE DbgCommRx Transmit*/ |
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29 | #define LPC22xx_INTERRUPT_TIMER0 4 /* Timer 0 */ |
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30 | #define LPC22xx_INTERRUPT_TIMER1 5 /* Timer 1 */ |
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31 | #define LPC22xx_INTERRUPT_UART0 6 /* UART 0 */ |
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32 | #define LPC22xx_INTERRUPT_UART1 7 /* UART 1 */ |
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33 | #define LPC22xx_INTERRUPT_PWM0 8 /* PWM */ |
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34 | #define LPC22xx_INTERRUPT_I2C 9 /* I2C */ |
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35 | #define LPC22xx_INTERRUPT_SPI0 10 /* SPI0 */ |
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36 | #define LPC22xx_INTERRUPT_SPI1 11 /* SPI1 */ |
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37 | #define LPC22xx_INTERRUPT_PLL 12 /* PLL */ |
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38 | #define LPC22xx_INTERRUPT_RTC 13 /* RTC */ |
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39 | #define LPC22xx_INTERRUPT_EINT0 14 /* Externel Interrupt 0 */ |
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40 | #define LPC22xx_INTERRUPT_EINT1 15 /* Externel Interrupt 1 */ |
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41 | #define LPC22xx_INTERRUPT_EINT2 16 /* Externel Interrupt 2 */ |
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42 | #define LPC22xx_INTERRUPT_EINT3 17 /* Externel Interrupt 3 */ |
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43 | #define LPC22xx_INTERRUPT_ADC 18 /* AD Converter */ |
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44 | /* Following interrupt used by lpc229x */ |
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45 | #define LPC22xx_INTERRUPT_CANERR 19 /* CAN LUTerr interrupt */ |
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46 | #define LPC22xx_INTERRUPT_CAN1TX 20 /* CAN1 Tx interrupt */ |
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47 | #define LPC22xx_INTERRUPT_CAN1RX 21 /* CAN1 Rx interrupt */ |
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48 | #define LPC22xx_INTERRUPT_CAN2TX 22 /* CAN2 Tx interrupt */ |
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49 | #define LPC22xx_INTERRUPT_CAN2RX 23 /* CAN2 Rx interrupt */ |
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50 | #define LPC22xx_INTERRUPT_CAN3TX 24 /* CAN1 Tx interrupt */ |
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51 | #define LPC22xx_INTERRUPT_CAN3RX 25 /* CAN1 Rx interrupt */ |
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52 | #define LPC22xx_INTERRUPT_CAN4TX 26 /* CAN2 Tx interrupt */ |
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53 | #define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ |
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54 | #define BSP_MAX_INT 28 |
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55 | |
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56 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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57 | |
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58 | #define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) |
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59 | |
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60 | #define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) |
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61 | #define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) |
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62 | #define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) |
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63 | #define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) |
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64 | #define IRQ_VECTOR_ADDR (*(u_long *)0x00000018L) |
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65 | #define FIQ_VECTOR_ADDR (*(u_long *)0x0000001CL) |
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66 | |
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67 | #define DATA_ABORT_ISR_ADDR (*(u_long *)0x00000030L) |
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68 | #define IRQ_ISR_ADDR (*(u_long *)0x00000038L) |
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69 | #define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) |
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70 | |
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71 | #endif /* __IRQ_H__ */ |
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