source: rtems/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h @ f4392b88

4.104.114.84.95
Last change on this file since f4392b88 was f4392b88, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 25, 2007 at 12:50:25 PM

2007-04-25 Ray Xu <xr@…>

  • Makefile.am, README, bsp_specs, configure.ac, console/lpc22xx_uart.h, console/uart.c, include/bsp.h, network/network.c: New (Initial submission).
  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 * Philips LPC22XX BSP header file
3 *
4 * by Ray,Xu
5 * 
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *
12 *  $Id$
13*/
14#ifndef _BSP_H
15#define _BSP_H
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#include <bspopts.h>
22
23#include <rtems.h>
24#include <rtems/iosupp.h>
25#include <rtems/console.h>
26#include <rtems/clockdrv.h>
27
28
29#define CONFIG_ARM_CLK 60000000L
30/* cclk=cco/(2*P) */
31/* cco = cclk*2*P       */
32
33#define LPC22xx_Fcclk   CONFIG_ARM_CLK  /* system clk frequecy,<=60Mhz, defined in system configuration */
34
35/* Fcco 156M~320Mhz*/
36#define LPC22xx_Fcclk   CONFIG_ARM_CLK  /* system clk frequecy,<=60Mhz, defined in system configuration */
37#define LPC22xx_Fcco    LPC22xx_Fcclk * 4
38#define LPC22xx_Fpclk   (LPC22xx_Fcclk /4) *1  /*VPB clk frequency,1,1/2,1/4 times of Fcclk */
39
40
41
42/* Fcclk range: 10MHz ~ MCU allowed frequency */
43#define Fcclk_MIN           10000000L
44#define Fcclk_MAX           60000000L
45
46/* Fcco range: 156MHz ~ 320MHz */
47#define Fcco_MIN            156000000L
48#define Fcco_MAX            320000000L
49
50#define PLLFEED_DATA1       0xAA
51#define PLLFEED_DATA2       0x55
52
53/* PLL PLLCON register bit descriptions */
54#define PLLCON_ENABLE_BIT   0
55#define PLLCON_CONNECT_BIT  1
56
57/* PLL PLLSTAT register bit descriptions */
58#define PLLSTAT_ENABLE_BIT  8
59#define PLLSTAT_CONNECT_BIT 9
60#define PLLSTAT_LOCK_BIT    10
61
62/* PM Peripheral Type */
63#define PC_TIMER0           0x2
64#define PC_TIMER1           0x4
65#define PC_UART0            0x8
66#define PC_UART1            0x10
67#define PC_PWM0             0x20
68#define PC_I2C              0x80
69#define PC_SPI0             0x100
70#define PC_RTC              0x200
71
72// OSC [Hz]
73#define FOSC              11059200
74// Core clk [Hz]
75#define FCCLK             FOSC<<2
76/**
77* help file
78*/
79/* ϵͳÉèÖÃ, Fosc¡¢Fcclk¡¢Fcco¡¢Fpclk±ØÐ붚Òå*/
80#define Fosc            11059200                    //Ÿ§ÕñƵÂÊ,10MHz~25MHz£¬ÓŠµ±ÓëʵŒÊÒ»ÖÁ
81#define Fcclk           (Fosc << 2)                  //ϵͳƵÂÊ£¬±ØÐëΪFoscµÄÕûÊý±¶(1~32)£¬ÇÒ<=60MHZ
82#define Fcco            (Fcclk <<2)                 //CCOƵÂÊ£¬±ØÐëΪFcclkµÄ2¡¢4¡¢8¡¢16±¶£¬·¶Î§Îª156MHz~320MHz
83#define Fpclk           (Fcclk >>2) * 1             //VPBʱÖÓƵÂÊ£¬Ö»ÄÜΪ(Fcclk / 4)µÄ1 ~ 4±¶
84#define M                Fcclk / Fosc;
85#define P_min         Fcco_MIN / (2*Fcclk) + 1;
86#define P_max        Fcco_MAX / (2*Fcclk);
87
88
89
90#define  UART_BPS       115200
91
92// Time Precision time [us]
93#define TIMER_PRECISION   10
94
95// I2C Speed [bit/s]
96#define I2CSPEED          20000         // 20 Kbit/s
97
98// Uarts buffers size
99#define RXBUFSIZE         32
100#define TXBUFSIZE         32
101
102// SPI Speed [bit/s]
103#define SPISPEED          1500000       // 1.5 Mbit/s
104// SPI EEPROM CS pin (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
105#define SPI_CS_PIN        P0_13
106#define SPI_CS_PIN_FUNC   PINSEL0_bit.SPI_CS_PIN
107
108// Flash definition
109//#define FLASH_SIZE              (0x200000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
110#define FLASH_SIZE              (0x80000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
111//#define FLASH_SIZE              (0x80000-FLASH_BOOT)      // Total area of Flash region in words 8 bit
112#define FLASH_BEGIN             0x80000000
113#define FLASH_BASE              (FLASH_BEGIN+FLASH_BOOT)   //First 0x8000 bytes reserved for boot loader etc.
114
115// SRAM definition
116#define SRAM_SIZE               0x100000                  // Total area of Flash region in words 8 bit
117#define SRAM_BASE               0x81000000                //First 0x8000 bytes reserved for boot loader etc.
118
119// CS8900A definition
120#define CS8900A_BASE            0x82000000                //
121// RTL8019AS definition
122#define RTL8019AS_BASE            0x82000000                //
123
124
125
126
127/*
128 *  Define the interrupt mechanism for Time Test 27
129 *
130 *  NOTE: Following are not defined and are board independent
131 *
132 */
133struct rtems_bsdnet_ifconfig;
134int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,
135                          int                          attaching);
136
137#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
138#define CONFIGURE_INTERRUPT_STACK_MEMORY  (1 * 1024)
139
140extern rtems_configuration_table BSP_Configuration;
141
142/*
143 * Network driver configuration
144 */
145#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
146#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
147
148#ifdef __cplusplus
149}
150#endif
151
152#endif /* _BSP_H */
Note: See TracBrowser for help on using the repository browser.