source: rtems/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h @ a3a6fae

4.104.115
Last change on this file since a3a6fae was a3a6fae, checked in by Joel Sherrill <joel.sherrill@…>, on 08/21/09 at 17:59:31

2009-08-21 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h: Eliminate BSPs defining NUMBER_OF_TERMIOS_PORTS. Should be automatically handled by confdefs.h or the application.
  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Philips LPC22XX/LPC21xx BSP header file
3 *
4 * by Ray,Xu <Rayx.cn@gmail.com>
5 * 
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *
12 *  $Id$
13*/
14#ifndef _BSP_H
15#define _BSP_H
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#include <bspopts.h>
22
23#include <rtems.h>
24#include <rtems/iosupp.h>
25#include <rtems/console.h>
26#include <rtems/clockdrv.h>
27
28
29#define CONFIG_ARM_CLK 60000000L
30/* cclk=cco/(2*P) */
31/* cco = cclk*2*P       */
32
33/* system clk frequecy,<=60Mhz, defined in system configuration */
34#define LPC22xx_Fcclk   CONFIG_ARM_CLK
35
36/* Fcco 156M~320Mhz*/
37/* system clk frequecy,<=60Mhz, defined in system configuration */
38#define LPC22xx_Fcclk   CONFIG_ARM_CLK
39#define LPC22xx_Fcco    LPC22xx_Fcclk * 4
40/*VPB clk frequency,1,1/2,1/4 times of Fcclk */
41#define LPC22xx_Fpclk   (LPC22xx_Fcclk /4) *1
42
43
44
45/* Fcclk range: 10MHz ~ MCU allowed frequency */
46#define Fcclk_MIN           10000000L
47#define Fcclk_MAX           60000000L
48
49/* Fcco range: 156MHz ~ 320MHz */
50#define Fcco_MIN            156000000L
51#define Fcco_MAX            320000000L
52
53#define PLLFEED_DATA1       0xAA
54#define PLLFEED_DATA2       0x55
55
56/* PLL PLLCON register bit descriptions */
57#define PLLCON_ENABLE_BIT   0
58#define PLLCON_CONNECT_BIT  1
59
60/* PLL PLLSTAT register bit descriptions */
61#define PLLSTAT_ENABLE_BIT  8
62#define PLLSTAT_CONNECT_BIT 9
63#define PLLSTAT_LOCK_BIT    10
64
65/* PM Peripheral Type */
66#define PC_TIMER0           0x2
67#define PC_TIMER1           0x4
68#define PC_UART0            0x8
69#define PC_UART1            0x10
70#define PC_PWM0             0x20
71#define PC_I2C              0x80
72#define PC_SPI0             0x100
73#define PC_RTC              0x200
74
75// OSC [Hz]
76#define FOSC              11059200
77// Core clk [Hz]
78#define FCCLK             FOSC<<2
79/**
80* help file
81*/
82/* System configure, Fosc Fcclk Fcco Fpclk must be defined*/
83#define Fosc    11059200          // osc freq,10MHz~25MHz,
84                                  //    change to real one if needed
85#define Fcclk   (Fosc << 2)       //system freq 2^n time of  Fosc(1~32) <=60MHZ
86#define Fcco    (Fcclk <<2)       //CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz
87#define Fpclk   (Fcclk >>2) * 1   //VPB freq only(Fcclk / 4) 1~4
88#define M       Fcclk / Fosc
89#define P_min   Fcco_MIN / (2*Fcclk) + 1;
90#define P_max   Fcco_MAX / (2*Fcclk);
91
92
93
94#define  UART_BPS       115200
95
96// Time Precision time [us]
97#define TIMER_PRECISION   10
98
99// I2C Speed [bit/s]
100#define I2CSPEED          20000         // 20 Kbit/s
101
102// Uarts buffers size
103#define RXBUFSIZE         32
104#define TXBUFSIZE         32
105
106// SPI Speed [bit/s]
107#define SPISPEED          1500000       // 1.5 Mbit/s
108// SPI EEPROM CS pin (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
109#define SPI_CS_PIN        P0_13
110#define SPI_CS_PIN_FUNC   PINSEL0_bit.SPI_CS_PIN
111
112// Flash definition
113//#define FLASH_SIZE      (0x200000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
114#define FLASH_SIZE        (0x80000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
115//#define FLASH_SIZE      (0x80000-FLASH_BOOT)      // Total area of Flash region in words 8 bit
116#define FLASH_BEGIN       0x80000000
117#define FLASH_BASE        (FLASH_BEGIN+FLASH_BOOT)   //First 0x8000 bytes reserved for boot loader etc.
118
119// SRAM definition
120#define SRAM_SIZE         0x100000                  // Total area of Flash region in words 8 bit
121#define SRAM_BASE         0x81000000                //First 0x8000 bytes reserved for boot loader etc.
122
123// CS8900A definition
124#define CS8900A_BASE      0x82000000
125// RTL8019AS definition
126#define RTL8019AS_BASE    0x82000000
127
128struct rtems_bsdnet_ifconfig;
129int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,
130                          int                          attaching);
131
132/*
133 * Network driver configuration
134 */
135#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
136#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
137
138#ifdef __cplusplus
139}
140#endif
141
142#endif /* _BSP_H */
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