1 | /** |
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2 | * @file |
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3 | * @ingroup arm_rtl22xx |
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4 | * @brief Global BSP definitions. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Philips LPC22XX/LPC21xx BSP header file |
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9 | * |
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10 | * by Ray,Xu <Rayx.cn@gmail.com> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | #ifndef _BSP_H |
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17 | #define _BSP_H |
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18 | |
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19 | #ifdef __cplusplus |
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20 | extern "C" { |
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21 | #endif |
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22 | |
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23 | #include <bspopts.h> |
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24 | #include <bsp/default-initial-extension.h> |
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25 | |
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26 | /** |
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27 | * @defgroup arm_rtl22xx RTL22XX Support |
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28 | * @ingroup bsp_arm |
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29 | * @brief RTL22XX Support Package |
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30 | * @{ |
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31 | */ |
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32 | |
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33 | #include <rtems.h> |
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34 | #include <rtems/iosupp.h> |
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35 | #include <rtems/console.h> |
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36 | #include <rtems/clockdrv.h> |
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37 | |
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38 | #define BSP_FEATURE_IRQ_EXTENSION |
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39 | |
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40 | #define CONFIG_ARM_CLK 60000000L |
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41 | /* cclk=cco/(2*P) */ |
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42 | /* cco = cclk*2*P */ |
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43 | |
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44 | /** @brief system clk frequecy,<=60Mhz, defined in system configuration */ |
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45 | #define LPC22xx_Fcclk CONFIG_ARM_CLK |
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46 | |
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47 | /* Fcco 156M~320Mhz*/ |
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48 | /** @brief system clk frequecy,<=60Mhz, defined in system configuration */ |
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49 | #define LPC22xx_Fcclk CONFIG_ARM_CLK |
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50 | #define LPC22xx_Fcco LPC22xx_Fcclk * 4 |
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51 | /** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ |
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52 | #define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 |
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53 | |
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54 | |
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55 | |
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56 | /** |
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57 | * @name Fcclk range: 10MHz ~ MCU allowed frequency |
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58 | * @{ |
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59 | */ |
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60 | |
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61 | #define Fcclk_MIN 10000000L |
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62 | #define Fcclk_MAX 60000000L |
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63 | |
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64 | /** @} */ |
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65 | |
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66 | /** |
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67 | * @name Fcco range: 156MHz ~ 320MHz |
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68 | * @{ |
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69 | */ |
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70 | |
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71 | #define Fcco_MIN 156000000L |
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72 | #define Fcco_MAX 320000000L |
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73 | |
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74 | /** @} */ |
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75 | |
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76 | #define PLLFEED_DATA1 0xAA |
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77 | #define PLLFEED_DATA2 0x55 |
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78 | |
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79 | /** |
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80 | * @name PLL PLLCON register bit descriptions |
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81 | * @{ |
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82 | */ |
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83 | |
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84 | #define PLLCON_ENABLE_BIT 0 |
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85 | #define PLLCON_CONNECT_BIT 1 |
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86 | |
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87 | /** @} */ |
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88 | |
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89 | /** |
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90 | * @name PLL PLLSTAT register bit descriptions |
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91 | * @{ |
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92 | */ |
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93 | |
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94 | #define PLLSTAT_ENABLE_BIT 8 |
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95 | #define PLLSTAT_CONNECT_BIT 9 |
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96 | #define PLLSTAT_LOCK_BIT 10 |
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97 | |
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98 | /** @} */ |
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99 | |
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100 | /** |
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101 | * @name PM Peripheral Type |
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102 | * @{ |
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103 | */ |
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104 | |
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105 | #define PC_TIMER0 0x2 |
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106 | #define PC_TIMER1 0x4 |
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107 | #define PC_UART0 0x8 |
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108 | #define PC_UART1 0x10 |
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109 | #define PC_PWM0 0x20 |
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110 | #define PC_I2C 0x80 |
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111 | #define PC_SPI0 0x100 |
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112 | #define PC_RTC 0x200 |
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113 | |
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114 | /** @} */ |
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115 | |
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116 | /** @brief OSC [Hz] */ |
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117 | #define FOSC 11059200 |
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118 | /** @brief Core clk [Hz] */ |
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119 | #define FCCLK FOSC<<2 |
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120 | |
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121 | /** |
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122 | * @name System Configure |
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123 | * @{ |
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124 | */ |
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125 | |
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126 | /** @brief osc freq,10MHz~25MHz, change to a real one if needed */ |
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127 | #define Fosc 11059200 |
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128 | /** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ |
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129 | #define Fcclk (Fosc << 2) |
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130 | /** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ |
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131 | #define Fcco (Fcclk <<2) |
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132 | /** @brief VPB freq only(Fcclk / 4) 1~4 */ |
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133 | #define Fpclk (Fcclk >>2) * 1 |
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134 | /* This was M. That is a BAD BAD public constant. I renamed it to |
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135 | * JOEL_M so it wouldn't conflict with user code. If you can find |
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136 | * a better name, fix this. But nothing I found uses it. |
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137 | */ |
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138 | |
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139 | /** @} */ |
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140 | |
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141 | #define JOEL_M Fcclk / Fosc |
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142 | #define P_min Fcco_MIN / (2*Fcclk) + 1; |
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143 | #define P_max Fcco_MAX / (2*Fcclk); |
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144 | |
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145 | #define UART_BPS 115200 |
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146 | |
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147 | /** @brief Time Precision time [us] */ |
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148 | #define TIMER_PRECISION 10 |
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149 | |
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150 | /** @brief I2C Speed [bit/s] */ |
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151 | #define I2CSPEED 20000 // 20 Kbit/s |
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152 | |
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153 | /** |
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154 | * @name Uarts buffers size |
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155 | * @{ |
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156 | */ |
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157 | |
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158 | #define RXBUFSIZE 32 |
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159 | #define TXBUFSIZE 32 |
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160 | |
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161 | /** @} */ |
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162 | |
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163 | /** @brief SPI Speed [bit/s] */ |
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164 | #define SPISPEED 1500000 // 1.5 Mbit/s |
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165 | /** @brief SPI EEPROM CS pin |
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166 | * |
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167 | * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) |
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168 | */ |
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169 | #define SPI_CS_PIN P0_13 |
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170 | #define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN |
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171 | |
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172 | /** |
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173 | * @name Flash definition |
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174 | * @{ |
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175 | */ |
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176 | |
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177 | //#define FLASH_SIZE (0x200000-FLASH_BOOT) // Total area of Flash region in words 8 bit |
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178 | /** @brief Total area of Flash region in words 8 bit */ |
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179 | #define FLASH_SIZE (0x80000-FLASH_BOOT) |
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180 | //#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit |
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181 | #define FLASH_BEGIN 0x80000000 |
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182 | /** @brief First 0x8000 bytes reserved for boot loader etc. */ |
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183 | #define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) |
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184 | |
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185 | /** @} */ |
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186 | |
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187 | /** |
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188 | * @name SRAM definition |
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189 | * @{ |
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190 | */ |
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191 | |
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192 | /** @brief Total area of Flash region in words 8 bit */ |
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193 | #define SRAM_SIZE 0x100000 |
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194 | /** @brief First 0x8000 bytes reserved for boot loader etc. */ |
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195 | #define SRAM_BASE 0x81000000 |
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196 | |
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197 | /** @} */ |
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198 | |
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199 | /** @brief CS8900A definition */ |
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200 | #define CS8900A_BASE 0x82000000 |
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201 | /** @brief RTL8019AS definition */ |
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202 | #define RTL8019AS_BASE 0x82000000 |
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203 | |
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204 | struct rtems_bsdnet_ifconfig; |
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205 | int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, |
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206 | int attaching); |
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207 | |
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208 | /** |
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209 | * @name Network driver configuration |
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210 | * @{ |
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211 | */ |
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212 | |
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213 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" |
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214 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach |
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215 | |
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216 | /** @} */ |
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217 | |
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218 | /** @} */ |
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219 | |
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220 | #ifdef __cplusplus |
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221 | } |
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222 | #endif |
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223 | |
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224 | #endif /* _BSP_H */ |
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