1 | /* |
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2 | * Definitions for LPC22xx/LPC21xx |
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3 | * |
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4 | * $Id$ |
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5 | */ |
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6 | |
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7 | #ifndef LPC22XX_UART_H |
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8 | #define LPC22XX_UART_H |
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9 | |
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10 | #define FIFODEEP 16 |
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11 | |
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12 | #define BD115200 115200 |
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13 | #define BD38400 38400 |
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14 | #define BD9600 9600 |
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15 | |
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16 | #define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */ |
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17 | #define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */ |
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18 | #define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */ |
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19 | #define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */ |
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20 | |
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21 | /* Uart line control register bit descriptions */ |
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22 | #define LCR_WORDLENTH_BIT 0 |
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23 | #define LCR_STOPBITSEL_BIT 2 |
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24 | #define LCR_PARITYENBALE_BIT 3 |
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25 | #define LCR_PARITYSEL_BIT 4 |
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26 | #define LCR_BREAKCONTROL_BIT 6 |
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27 | #define LCR_DLAB_BIT 7 |
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28 | // Line Control Register bit definitions |
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29 | #define ULCR_CHAR_5 (0 << 0) // 5-bit character length |
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30 | #define ULCR_CHAR_6 (1 << 0) // 6-bit character length |
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31 | #define ULCR_CHAR_7 (2 << 0) // 7-bit character length |
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32 | #define ULCR_CHAR_8 (3 << 0) // 8-bit character length |
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33 | #define ULCR_STOP_0 (0 << 2) // no stop bits |
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34 | #define ULCR_STOP_1 (1 << 2) // 1 stop bit |
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35 | #define ULCR_PAR_NO (0 << 3) // No Parity |
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36 | #define ULCR_PAR_ODD (1 << 3) // Odd Parity |
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37 | #define ULCR_PAR_EVEN (3 << 3) // Even Parity |
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38 | #define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity |
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39 | #define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty |
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40 | #define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition |
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41 | #define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access |
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42 | // Modem Control Register bit definitions |
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43 | #define UMCR_DTR (1 << 0) // Data Terminal Ready |
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44 | #define UMCR_RTS (1 << 1) // Request To Send |
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45 | #define UMCR_LB (1 << 4) // Loopback |
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46 | |
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47 | // Line Status Register bit definitions |
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48 | #define ULSR_RDR (1 << 0) // Receive Data Ready |
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49 | #define ULSR_OE (1 << 1) // Overrun Error |
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50 | #define ULSR_PE (1 << 2) // Parity Error |
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51 | #define ULSR_FE (1 << 3) // Framing Error |
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52 | #define ULSR_BI (1 << 4) // Break Interrupt |
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53 | #define ULSR_THRE (1 << 5) // Transmit Holding Register Empty |
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54 | #define ULSR_TEMT (1 << 6) // Transmitter Empty |
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55 | #define ULSR_RXFE (1 << 7) // Error in Receive FIFO |
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56 | #define ULSR_ERR_MASK 0x1E |
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57 | |
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58 | // Modem Status Register bit definitions |
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59 | #define UMSR_DCTS (1 << 0) // Delta Clear To Send |
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60 | #define UMSR_DDSR (1 << 1) // Delta Data Set Ready |
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61 | #define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator |
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62 | #define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect |
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63 | #define UMSR_CTS (1 << 4) // Clear To Send |
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64 | #define UMSR_DSR (1 << 5) // Data Set Ready |
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65 | #define UMSR_RI (1 << 6) // Ring Indicator |
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66 | #define UMSR_DCD (1 << 7) // Data Carrier Detect |
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67 | |
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68 | /* Uart Interrupt Identification */ |
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69 | #define IIR_RSL 0x3 |
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70 | #define IIR_RDA 0x2 |
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71 | #define IIR_CTI 0x6 |
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72 | #define IIR_THRE 0x1 |
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73 | |
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74 | /* Uart Interrupt Enable Type*/ |
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75 | #define IER_RBR 0x1 |
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76 | #define IER_THRE 0x2 |
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77 | #define IER_RLS 0x4 |
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78 | |
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79 | /* Uart Receiver Errors*/ |
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80 | #define RC_FIFO_OVERRUN_ERR 0x1 |
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81 | #define RC_OVERRUN_ERR 0x2 |
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82 | #define RC_PARITY_ERR 0x4 |
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83 | #define RC_FRAMING_ERR 0x8 |
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84 | #define RC_BREAK_IND 0x10 |
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85 | |
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86 | typedef enum { |
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87 | UART0 = 0, |
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88 | UART1 |
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89 | } LPC_UartChanel_t; |
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90 | #endif |
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91 | |
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