source: rtems/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h @ 9b4422a2

4.11
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  Definitions for LPC22xx/LPC21xx
3 */
4
5#ifndef LPC22XX_UART_H
6#define LPC22XX_UART_H
7
8#define FIFODEEP    16
9
10#define BD115200    115200
11#define BD38400     38400
12#define BD9600      9600
13
14#define U0_PINSEL       (0x00000005)    /* PINSEL0 Value for UART0 */
15#define U0_PINMASK      (0x0000000F)    /* PINSEL0 Mask for UART0 */
16#define U1_PINSEL       (0x00050000)    /* PINSEL0 Value for UART1 */
17#define U1_PINMASK      (0x000F0000)    /* PINSEL0 Mask for UART1 */
18
19/* Uart line control register bit descriptions */
20#define LCR_WORDLENTH_BIT         0
21#define LCR_STOPBITSEL_BIT        2
22#define LCR_PARITYENBALE_BIT      3
23#define LCR_PARITYSEL_BIT         4
24#define LCR_BREAKCONTROL_BIT      6
25#define LCR_DLAB_BIT              7
26// Line Control Register bit definitions
27#define ULCR_CHAR_5         (0 << 0)    // 5-bit character length
28#define ULCR_CHAR_6         (1 << 0)    // 6-bit character length
29#define ULCR_CHAR_7         (2 << 0)    // 7-bit character length
30#define ULCR_CHAR_8         (3 << 0)    // 8-bit character length
31#define ULCR_STOP_0         (0 << 2)    // no stop bits
32#define ULCR_STOP_1         (1 << 2)    // 1 stop bit
33#define ULCR_PAR_NO         (0 << 3)    // No Parity
34#define ULCR_PAR_ODD        (1 << 3)    // Odd Parity
35#define ULCR_PAR_EVEN       (3 << 3)    // Even Parity
36#define ULCR_PAR_MARK       (5 << 3)    // MARK "1" Parity
37#define ULCR_PAR_SPACE      (7 << 3)    // SPACE "0" Paruty
38#define ULCR_BREAK_ENABLE   (1 << 6)    // Output BREAK line condition
39#define ULCR_DLAB_ENABLE    (1 << 7)    // Enable Divisor Latch Access
40// Modem Control Register bit definitions
41#define UMCR_DTR            (1 << 0)    // Data Terminal Ready
42#define UMCR_RTS            (1 << 1)    // Request To Send
43#define UMCR_LB             (1 << 4)    // Loopback
44
45// Line Status Register bit definitions
46#define ULSR_RDR            (1 << 0)    // Receive Data Ready
47#define ULSR_OE             (1 << 1)    // Overrun Error
48#define ULSR_PE             (1 << 2)    // Parity Error
49#define ULSR_FE             (1 << 3)    // Framing Error
50#define ULSR_BI             (1 << 4)    // Break Interrupt
51#define ULSR_THRE           (1 << 5)    // Transmit Holding Register Empty
52#define ULSR_TEMT           (1 << 6)    // Transmitter Empty
53#define ULSR_RXFE           (1 << 7)    // Error in Receive FIFO
54#define ULSR_ERR_MASK       0x1E
55
56// Modem Status Register bit definitions
57#define UMSR_DCTS           (1 << 0)    // Delta Clear To Send
58#define UMSR_DDSR           (1 << 1)    // Delta Data Set Ready
59#define UMSR_TERI           (1 << 2)    // Trailing Edge Ring Indicator
60#define UMSR_DDCD           (1 << 3)    // Delta Data Carrier Detect
61#define UMSR_CTS            (1 << 4)    // Clear To Send
62#define UMSR_DSR            (1 << 5)    // Data Set Ready
63#define UMSR_RI             (1 << 6)    // Ring Indicator
64#define UMSR_DCD            (1 << 7)    // Data Carrier Detect
65
66/* Uart Interrupt Identification */
67#define IIR_RSL                   0x3
68#define IIR_RDA                   0x2
69#define IIR_CTI                   0x6
70#define IIR_THRE                  0x1
71
72/* Uart Interrupt Enable Type*/
73#define IER_RBR                   0x1
74#define IER_THRE                  0x2
75#define IER_RLS                   0x4
76
77/* Uart Receiver Errors*/
78#define RC_FIFO_OVERRUN_ERR       0x1
79#define RC_OVERRUN_ERR            0x2
80#define RC_PARITY_ERR             0x4
81#define RC_FRAMING_ERR            0x8
82#define RC_BREAK_IND              0x10
83
84typedef enum {
85  UART0 = 0,
86  UART1
87} LPC_UartChanel_t;
88#endif
89
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