source: rtems/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h @ 78e529a6

4.11
Last change on this file since 78e529a6 was 78e529a6, checked in by Daniel Ramirez <javamonn@…>, on Dec 22, 2013 at 7:49:52 PM

arm_rtl22xx: added new doxygen

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/**
2 * @file
3 * @ingroup rtl22xx_uart
4 * @brief UART support.
5 */
6
7#ifndef LPC22XX_UART_H
8#define LPC22XX_UART_H
9
10/**
11 * @defgroup rtl22xx_uart UART Support
12 * @ingroup arm_rtl22xx
13 * @brief UART (Universal Asynchronous Reciever/Transmitter) Support
14 * @{
15 */
16
17#define FIFODEEP    16
18
19#define BD115200    115200
20#define BD38400     38400
21#define BD9600      9600
22
23/** @brief PINSEL0 Value for UART0 */
24#define U0_PINSEL       (0x00000005)
25/** @brief PINSEL0 Mask for UART0 */
26#define U0_PINMASK      (0x0000000F)
27/** @brief PINSEL0 Value for UART1 */
28#define U1_PINSEL       (0x00050000)
29/** @brief PINSEL0 Mask for UART1 */
30#define U1_PINMASK      (0x000F0000)
31
32/**
33 * @name Uart line control register bit descriptions
34 * @{
35 */
36
37#define LCR_WORDLENTH_BIT         0
38#define LCR_STOPBITSEL_BIT        2
39#define LCR_PARITYENBALE_BIT      3
40#define LCR_PARITYSEL_BIT         4
41#define LCR_BREAKCONTROL_BIT      6
42#define LCR_DLAB_BIT              7
43
44/** @} */
45
46/**
47 * @name Line Control Register bit definitions
48 * @{
49 */
50
51/** @brief 5-bit character length */
52#define ULCR_CHAR_5         (0 << 0)
53/** @brief 6-bit character length */
54#define ULCR_CHAR_6         (1 << 0)
55/** @brief 7-bit character length */
56#define ULCR_CHAR_7         (2 << 0)
57/** @brief 8-bit character length */
58#define ULCR_CHAR_8         (3 << 0)
59/** @brief no stop bits */
60#define ULCR_STOP_0         (0 << 2)
61/** @brief 1 stop bit */
62#define ULCR_STOP_1         (1 << 2)
63/** @brief No Parity */
64#define ULCR_PAR_NO         (0 << 3)
65/** @brief Odd Parity */
66#define ULCR_PAR_ODD        (1 << 3)
67/** @brief Even Parity */
68#define ULCR_PAR_EVEN       (3 << 3)
69/** @brief MARK "1" Parity */
70#define ULCR_PAR_MARK       (5 << 3)
71/** @brief SPACE "0" Paruty */
72#define ULCR_PAR_SPACE      (7 << 3)
73/** @brief Output BREAK line condition */
74#define ULCR_BREAK_ENABLE   (1 << 6)
75/** @brief Enable Divisor Latch Access */
76#define ULCR_DLAB_ENABLE    (1 << 7)
77
78/** @} */
79
80/**
81 * @name Modem Control Register bit definitions
82 * @{
83 */
84
85/** @brief Data Terminal Ready */
86#define UMCR_DTR            (1 << 0)
87/** @brief Request To Send */
88#define UMCR_RTS            (1 << 1)
89/** @brief Loopback */
90#define UMCR_LB             (1 << 4)
91
92/** @} */
93
94/**
95 * @name  Line Status Register bit definitions
96 * @{
97 */
98
99/** @brief Receive Data Ready */
100#define ULSR_RDR            (1 << 0)
101/** @brief Overrun Error */
102#define ULSR_OE             (1 << 1)
103/** @brief Parity Error */
104#define ULSR_PE             (1 << 2)
105/** @brief Framing Error */
106#define ULSR_FE             (1 << 3)
107/** @brief Break Interrupt */
108#define ULSR_BI             (1 << 4)
109/** @brief Transmit Holding Register Empty */
110#define ULSR_THRE           (1 << 5)
111/** @brief Transmitter Empty */
112#define ULSR_TEMT           (1 << 6)
113/** @brief Error in Receive FIFO */
114#define ULSR_RXFE           (1 << 7)
115#define ULSR_ERR_MASK       0x1E
116
117/** @} */
118
119/**
120 * @name Modem Status Register bit definitions
121 * @{
122 */
123
124/** @brief Delta Clear To Send */
125#define UMSR_DCTS           (1 << 0)
126/** @brief Delta Data Set Ready */
127#define UMSR_DDSR           (1 << 1)
128/** @brief Trailing Edge Ring Indicator */
129#define UMSR_TERI           (1 << 2)
130/** @brief Delta Data Carrier Detect */
131#define UMSR_DDCD           (1 << 3)
132/** @brief Clear To Send */
133#define UMSR_CTS            (1 << 4)
134/** @brief Data Set Ready */
135#define UMSR_DSR            (1 << 5)
136/** @brief Ring Indicator */
137#define UMSR_RI             (1 << 6)
138/** @brief Data Carrier Detect */
139#define UMSR_DCD            (1 << 7)
140
141/** @} */
142
143/**
144 * @name Uart Interrupt Identification
145 * @{
146 */
147
148#define IIR_RSL                   0x3
149#define IIR_RDA                   0x2
150#define IIR_CTI                   0x6
151#define IIR_THRE                  0x1
152
153/** @} */
154
155/**
156 * @name  Uart Interrupt Enable Type
157 * @{
158 */
159
160#define IER_RBR                   0x1
161#define IER_THRE                  0x2
162#define IER_RLS                   0x4
163
164/** @} */
165
166/**
167 * @name Uart Receiver Errors
168 * @{
169 */
170
171#define RC_FIFO_OVERRUN_ERR       0x1
172#define RC_OVERRUN_ERR            0x2
173#define RC_PARITY_ERR             0x4
174#define RC_FRAMING_ERR            0x8
175#define RC_BREAK_IND              0x10
176
177/** @} */
178
179typedef enum {
180  UART0 = 0,
181  UART1
182} LPC_UartChanel_t;
183
184/** @} */
185
186#endif
187
Note: See TracBrowser for help on using the repository browser.