1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_start |
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5 | * |
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6 | * @brief Rasberry Pi startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013. Hesham AL-Matary |
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11 | * Copyright (c) 2013 by Alan Cudmore |
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12 | * based on work by: |
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13 | * Copyright (c) 2009 |
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14 | * embedded brains GmbH |
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15 | * Obere Lagerstr. 30 |
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16 | * D-82178 Puchheim |
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17 | * Germany |
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18 | * <rtems@embedded-brains.de> |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE |
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23 | */ |
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24 | |
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25 | #include <bspopts.h> |
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26 | #include <bsp/start.h> |
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27 | #include <bsp/raspberrypi.h> |
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28 | #include <bsp/mm.h> |
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29 | #include <libcpu/arm-cp15.h> |
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30 | #include <bsp.h> |
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31 | |
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32 | #ifdef RTEMS_SMP |
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33 | #include <rtems/score/smp.h> |
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34 | #endif |
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35 | |
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36 | void BSP_START_TEXT_SECTION bsp_start_hook_0(void) |
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37 | { |
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38 | uint32_t sctlr_val; |
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39 | #ifdef RTEMS_SMP |
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40 | uint32_t cpu_index_self = _SMP_Get_current_processor(); |
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41 | #endif /* RTEMS_SMP */ |
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42 | |
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43 | sctlr_val = arm_cp15_get_control(); |
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44 | |
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45 | /* |
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46 | * Current U-boot loader seems to start kernel image |
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47 | * with I and D caches on and MMU enabled. |
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48 | * If RTEMS application image finds that cache is on |
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49 | * during startup then disable caches. |
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50 | */ |
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51 | if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) { |
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52 | if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) { |
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53 | /* |
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54 | * If the data cache is on then ensure that it is clean |
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55 | * before switching off to be extra carefull. |
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56 | */ |
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57 | #ifdef RTEMS_SMP |
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58 | if (cpu_index_self != 0) { |
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59 | arm_cp15_data_cache_clean_level(0); |
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60 | arm_cp15_cache_invalidate_level(0, 0); |
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61 | } else |
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62 | #endif /* RTEMS_SMP */ |
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63 | { |
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64 | rtems_cache_flush_entire_data(); |
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65 | rtems_cache_invalidate_entire_data(); |
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66 | } |
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67 | } |
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68 | arm_cp15_flush_prefetch_buffer(); |
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69 | sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A); |
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70 | arm_cp15_set_control(sctlr_val); |
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71 | } |
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72 | #ifdef RTEMS_SMP |
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73 | if (cpu_index_self != 0) { |
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74 | arm_cp15_cache_invalidate_level(0, 0); |
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75 | } else |
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76 | #endif /* RTEMS_SMP */ |
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77 | { |
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78 | rtems_cache_invalidate_entire_data(); |
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79 | } |
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80 | rtems_cache_invalidate_entire_instruction(); |
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81 | arm_cp15_branch_predictor_invalidate_all(); |
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82 | arm_cp15_tlb_invalidate(); |
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83 | arm_cp15_flush_prefetch_buffer(); |
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84 | |
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85 | /* Clear Translation Table Base Control Register */ |
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86 | arm_cp15_set_translation_table_base_control_register(0); |
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87 | |
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88 | /* Clear Secure or Non-secure Vector Base Address Register */ |
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89 | arm_cp15_set_vector_base_address(0); |
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90 | |
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91 | #ifdef RTEMS_SMP |
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92 | if (cpu_index_self == 0) { |
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93 | rpi_ipi_initialize(); |
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94 | } else { |
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95 | rpi_start_rtems_on_secondary_processor(); |
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96 | } |
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97 | #endif |
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98 | } |
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99 | |
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100 | void BSP_START_TEXT_SECTION bsp_start_hook_1(void) |
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101 | { |
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102 | bsp_start_copy_sections(); |
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103 | bsp_memory_management_initialize(); |
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104 | bsp_start_clear_bss(); |
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105 | |
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106 | rpi_video_init(); |
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107 | } |
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