[7aca0fe] | 1 | /** |
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| 2 | * @file i2c.c |
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| 3 | * |
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| 4 | * @ingroup raspberrypi_i2c |
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| 5 | * |
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| 6 | * @brief Support for the I2C bus on the Raspberry Pi GPIO P1 header (model A/B) |
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| 7 | * and GPIO J8 header on model B+. |
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| 8 | */ |
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| 9 | |
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| 10 | /* |
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| 11 | * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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| 15 | * http://www.rtems.org/license/LICENSE. |
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| 16 | */ |
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| 17 | |
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| 18 | /* |
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| 19 | * STATUS: |
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| 20 | * - 10-bit slave addressing untested |
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| 21 | */ |
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| 22 | |
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| 23 | #include <bsp.h> |
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| 24 | #include <bsp/raspberrypi.h> |
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| 25 | #include <bsp/gpio.h> |
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| 26 | #include <bsp/rpi-gpio.h> |
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| 27 | #include <bsp/irq.h> |
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| 28 | #include <bsp/i2c.h> |
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| 29 | #include <assert.h> |
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| 30 | |
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| 31 | #define TRANSFER_COUNT(buffer_size) (buffer_size + 0xFFFE) / 0xFFFF |
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| 32 | |
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| 33 | #define ADJUST_TRANSFER_SIZE(transfer_count, remaining_bytes) \ |
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| 34 | transfer_count > 1 ? 0xFFFF : (remaining_bytes & 0xFFFF) |
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| 35 | |
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| 36 | #define I2C_POLLING(condition) \ |
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| 37 | while ( condition ) { \ |
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| 38 | ; \ |
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| 39 | } |
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| 40 | |
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| 41 | /** |
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| 42 | * @brief Object containing relevant information about an I2C bus. |
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| 43 | * |
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| 44 | * Encapsulates relevant data for a I2C bus transfer. |
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| 45 | */ |
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| 46 | typedef struct |
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| 47 | { |
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| 48 | i2c_bus base; |
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| 49 | uint32_t input_clock; |
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| 50 | rtems_id task_id; |
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| 51 | |
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| 52 | /* Remaining bytes to read/write on the current bus transfer. */ |
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| 53 | uint32_t remaining_bytes; |
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| 54 | /* Each transfer has a limit of 0xFFFF bytes, hence larger transfers |
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| 55 | * have to be divided. Each transfer implies a stop condition, signaled |
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| 56 | * automatically by the BSC controller. */ |
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| 57 | uint32_t remaining_transfers; |
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| 58 | |
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| 59 | uint8_t *current_buffer; |
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| 60 | uint32_t current_buffer_size; |
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| 61 | |
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| 62 | bool read_transfer; |
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| 63 | } rpi_i2c_bus; |
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| 64 | |
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| 65 | static int rpi_i2c_bus_transfer(rpi_i2c_bus *bus) |
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| 66 | { |
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| 67 | while ( bus->remaining_bytes >= 1 ) { |
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| 68 | /* If reading. */ |
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| 69 | if ( bus->read_transfer ) { |
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| 70 | /* Poll RXD bit until there is data on the RX FIFO to read. */ |
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| 71 | I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 5)) == 0); |
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| 72 | |
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| 73 | /* Read data from the RX FIFO. */ |
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| 74 | (*(uint8_t *) bus->current_buffer) = BCM2835_REG(BCM2835_I2C_FIFO) & 0xFF; |
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| 75 | |
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| 76 | ++bus->current_buffer; |
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| 77 | |
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| 78 | /* Check for acknowledgment or clock stretching errors. */ |
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| 79 | if ( |
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| 80 | (BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) || |
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| 81 | (BCM2835_REG(BCM2835_I2C_S) & (1 << 9)) |
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| 82 | ) { |
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| 83 | return -EIO; |
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| 84 | } |
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| 85 | } |
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| 86 | /* If writing. */ |
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| 87 | else { |
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| 88 | /* If using the I2C bus in interrupt-driven mode. */ |
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| 89 | #if I2C_IO_MODE == 1 |
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| 90 | /* Generate interrupts on the TXW bit condition. */ |
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| 91 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 9); |
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| 92 | |
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| 93 | /* Sleep until the TX FIFO has free space for a new write. */ |
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[4200a36a] | 94 | bus->task_id = rtems_task_self(); |
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[7aca0fe] | 95 | if ( |
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| 96 | rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout) != |
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| 97 | RTEMS_SUCCESSFUL |
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| 98 | ) { |
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| 99 | rtems_event_transient_clear(); |
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| 100 | |
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| 101 | return -ETIMEDOUT; |
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| 102 | } |
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| 103 | |
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| 104 | /* If using the bus in polling mode. */ |
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| 105 | #else |
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| 106 | /* Poll TXW bit until there is space available to write. */ |
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| 107 | I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 2)) == 0); |
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| 108 | #endif |
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| 109 | |
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| 110 | /* Write data to the TX FIFO. */ |
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| 111 | BCM2835_REG(BCM2835_I2C_FIFO) = (*(uint8_t *) bus->current_buffer); |
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| 112 | |
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| 113 | ++bus->current_buffer; |
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| 114 | |
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| 115 | /* Check for acknowledgment or clock stretching errors. */ |
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| 116 | if ( |
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| 117 | (BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) || |
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| 118 | (BCM2835_REG(BCM2835_I2C_S) & (1 << 9)) |
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| 119 | ) { |
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| 120 | return -EIO; |
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| 121 | } |
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| 122 | } |
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| 123 | |
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| 124 | --bus->remaining_bytes; |
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| 125 | --bus->current_buffer_size; |
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| 126 | } |
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| 127 | |
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| 128 | return 0; |
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| 129 | } |
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| 130 | |
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| 131 | static int rpi_i2c_setup_transfer(rpi_i2c_bus *bus) |
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| 132 | { |
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| 133 | int rv; |
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| 134 | |
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| 135 | while ( bus->remaining_transfers > 0 ) { |
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| 136 | /* Setup the byte size of the current transfer. */ |
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| 137 | bus->remaining_bytes = ADJUST_TRANSFER_SIZE( |
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| 138 | bus->remaining_transfers, |
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| 139 | bus->current_buffer_size |
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| 140 | ); |
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| 141 | |
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| 142 | /* Set the DLEN register, which specifies how many data packets |
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| 143 | * will be transferred. */ |
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| 144 | BCM2835_REG(BCM2835_I2C_DLEN) = bus->remaining_bytes; |
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| 145 | |
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| 146 | /* Clear the acknowledgment and clock stretching error status. */ |
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| 147 | BCM2835_REG(BCM2835_I2C_S) |= (3 << 8); |
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| 148 | |
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| 149 | /* Send start bit. */ |
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| 150 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 7); |
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| 151 | |
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| 152 | /* Check for an acknowledgment error. */ |
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| 153 | if ( (BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) != 0 ) { |
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| 154 | return -EIO; |
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| 155 | } |
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| 156 | |
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| 157 | rv = rpi_i2c_bus_transfer(bus); |
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| 158 | |
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| 159 | if ( rv < 0 ) { |
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| 160 | return rv; |
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| 161 | } |
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| 162 | |
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| 163 | /* Wait for the current transfer to finish. */ |
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| 164 | |
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| 165 | /* If using the I2C bus in interrupt-driven mode. */ |
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| 166 | #if I2C_IO_MODE == 1 |
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| 167 | /* Generate interrupts on the DONE bit condition. */ |
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| 168 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 8); |
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| 169 | |
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| 170 | if ( |
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| 171 | rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout) != |
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| 172 | RTEMS_SUCCESSFUL |
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| 173 | ) { |
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| 174 | rtems_event_transient_clear(); |
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| 175 | |
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| 176 | return -ETIMEDOUT; |
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| 177 | } |
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| 178 | /* If using the bus in polling mode. */ |
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| 179 | #else |
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| 180 | /* Poll DONE bit until all data has been sent. */ |
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| 181 | I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 1)) == 0); |
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| 182 | #endif |
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| 183 | |
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| 184 | --bus->remaining_transfers; |
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| 185 | } |
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| 186 | |
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| 187 | return 0; |
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| 188 | } |
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| 189 | |
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| 190 | /* Handler function that is called on any I2C interrupt. |
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| 191 | * |
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| 192 | * There are 3 situations that can generate an interrupt: |
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| 193 | * |
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| 194 | * 1. Transfer (read/write) complete; |
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| 195 | * 2. The TX FIFO has space for more data (during a write transfer); |
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| 196 | * 3. The RX FIFO is full. |
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| 197 | * |
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| 198 | * Because the I2C FIFO has a 16 byte size, the 3. situation is not |
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| 199 | * as useful to many applications as knowing that at least 1 byte can |
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| 200 | * be read from the RX FIFO. For that reason this information is |
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| 201 | * got through polling the RXD bit even in interrupt-driven mode. |
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| 202 | * |
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| 203 | * This leaves only 2 interrupts to be caught. At any given time |
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| 204 | * when no I2C bus transfer is taking place no I2C interrupts are |
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| 205 | * generated, and they do they are only enabled one at a time: |
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| 206 | * |
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| 207 | * - When trying to write, the 2. interrupt is enabled to signal that |
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| 208 | * data can be written on the TX FIFO, avoiding data loss in case |
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| 209 | * it is full. When caught the handler disables that interrupt from |
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| 210 | * being generated and sends a waking event to the transfer task, |
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| 211 | * which will allow the transfer process to continue |
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| 212 | * (by writing to the TX FIFO); |
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| 213 | * |
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| 214 | * - When the transfer is done on the Raspberry side, the 1. interrupt is |
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| 215 | * enabled for the device to signal it has finished the transfer as |
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| 216 | * well. When caught the handler disables that interrupt from being |
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| 217 | * generated and sends a waking event to the transfer task, marking |
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| 218 | * the end of the transfer. |
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| 219 | */ |
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| 220 | #if I2C_IO_MODE == 1 |
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| 221 | static void i2c_handler(void *arg) |
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| 222 | { |
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| 223 | rpi_i2c_bus *bus = (rpi_i2c_bus *) arg; |
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| 224 | |
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| 225 | /* If the current enabled interrupt is on the TXW condition, disable it. */ |
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| 226 | if ( (BCM2835_REG(BCM2835_I2C_C) & (1 << 9)) ) { |
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| 227 | BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 9); |
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| 228 | } |
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| 229 | /* If the current enabled interrupt is on the DONE condition, disable it. */ |
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| 230 | else if ( (BCM2835_REG(BCM2835_I2C_C) & (1 << 8)) ) { |
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| 231 | BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 8); |
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| 232 | } |
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| 233 | |
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| 234 | /* Allow the transfer process to continue. */ |
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| 235 | rtems_event_transient_send(bus->task_id); |
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| 236 | } |
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| 237 | #endif |
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| 238 | |
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| 239 | static int rpi_i2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t msg_count) |
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| 240 | { |
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| 241 | rpi_i2c_bus *bus = (rpi_i2c_bus *) base; |
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[70e8abf] | 242 | int rv = 0; |
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[7aca0fe] | 243 | uint32_t i; |
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| 244 | |
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| 245 | /* Perform an initial parse through the messages for the I2C_M_RECV_LEN flag, |
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| 246 | * which the Pi seems to not support and the I2C framework expects the bus |
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| 247 | * to provide as part of the I2C_FUNC_I2C functionality. |
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| 248 | * |
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| 249 | * It states that the slave device sends an initial byte containing the size |
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| 250 | * of the transfer, and for this to work the Pi will likely require two |
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| 251 | * transfers, with a stop-start condition in-between. */ |
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| 252 | for ( i = 0; i < msg_count; ++i ) { |
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| 253 | if ( msgs[i].flags & I2C_M_RECV_LEN ) { |
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| 254 | return -EINVAL; |
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| 255 | } |
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| 256 | } |
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| 257 | |
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| 258 | for ( i = 0; i < msg_count; ++i ) { |
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| 259 | /* Clear FIFOs. */ |
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| 260 | BCM2835_REG(BCM2835_I2C_C) |= (3 << 4); |
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| 261 | |
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| 262 | /* Setup transfer. */ |
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| 263 | bus->current_buffer = msgs[i].buf; |
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| 264 | bus->current_buffer_size = msgs[i].len; |
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| 265 | bus->remaining_transfers = TRANSFER_COUNT(bus->current_buffer_size); |
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| 266 | |
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| 267 | /* If the slave uses 10-bit addressing. */ |
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| 268 | if ( msgs[i].flags & I2C_M_TEN ) { |
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| 269 | /* Write the 8 least-significative bits of the slave address |
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| 270 | * to the bus FIFO. */ |
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| 271 | BCM2835_REG(BCM2835_I2C_FIFO) = msgs[i].addr & 0xFF; |
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| 272 | |
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| 273 | /* Address slave device, with the 2 most-significative bits at the end. */ |
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| 274 | BCM2835_REG(BCM2835_I2C_A) = (0x1E << 2) | (msgs[i].addr >> 8); |
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| 275 | } |
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| 276 | /* If using the regular 7-bit slave addressing. */ |
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| 277 | else { |
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| 278 | /* Address slave device. */ |
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| 279 | BCM2835_REG(BCM2835_I2C_A) = msgs[i].addr; |
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| 280 | } |
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| 281 | |
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| 282 | if ( msgs[i].flags & I2C_M_RD ) { |
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| 283 | /* If the slave uses 10-bit addressing. */ |
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| 284 | if ( msgs[i].flags & I2C_M_TEN ) { |
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| 285 | /* 10-bit addressing setup for a read transfer. */ |
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| 286 | BCM2835_REG(BCM2835_I2C_DLEN) = 1; |
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| 287 | |
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| 288 | /* Set write bit. */ |
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| 289 | BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 0); |
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| 290 | |
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| 291 | /* Send start bit. */ |
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| 292 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 7); |
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| 293 | |
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| 294 | /* Poll the TA bit until the transfer has started. */ |
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| 295 | I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 0)) == 0); |
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| 296 | } |
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| 297 | |
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| 298 | /* Set read bit. */ |
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| 299 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 0); |
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| 300 | |
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| 301 | bus->read_transfer = true; |
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| 302 | } |
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| 303 | else if ( msgs[i].flags == 0 || msgs[i].flags == I2C_M_TEN ) { |
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| 304 | /* If the slave uses 10-bit addressing. */ |
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| 305 | if ( msgs[i].flags & I2C_M_TEN ) { |
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| 306 | /* 10-bit addressing setup for a write transfer. */ |
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| 307 | bus->current_buffer_size += 1; |
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| 308 | |
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| 309 | bus->remaining_transfers = TRANSFER_COUNT(bus->current_buffer_size); |
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| 310 | } |
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| 311 | |
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| 312 | /* Set write bit. */ |
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| 313 | BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 0); |
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| 314 | |
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| 315 | bus->read_transfer = false; |
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| 316 | } |
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| 317 | |
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| 318 | rv = rpi_i2c_setup_transfer(bus); |
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| 319 | |
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| 320 | if ( rv < 0 ) { |
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| 321 | return rv; |
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| 322 | } |
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| 323 | } |
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| 324 | |
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| 325 | return rv; |
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| 326 | } |
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| 327 | |
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| 328 | /* Calculates a clock divider to be used with the BSC core clock rate |
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| 329 | * to set a I2C clock rate the closest (<=) to a desired frequency. */ |
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| 330 | static int rpi_i2c_set_clock(i2c_bus *base, unsigned long clock) |
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| 331 | { |
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| 332 | rpi_i2c_bus *bus = (rpi_i2c_bus *) base; |
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| 333 | uint32_t clock_rate; |
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| 334 | uint16_t divider; |
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| 335 | |
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| 336 | /* Calculates an initial clock divider. */ |
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| 337 | divider = BSC_CORE_CLK_HZ / clock; |
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| 338 | |
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| 339 | clock_rate = BSC_CORE_CLK_HZ / divider; |
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| 340 | |
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| 341 | /* If the resulting clock rate is greater than desired, try the next greater |
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| 342 | * divider. */ |
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| 343 | while ( clock_rate > clock ) { |
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| 344 | ++divider; |
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| 345 | |
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| 346 | clock_rate = BSC_CORE_CLK_HZ / divider; |
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| 347 | } |
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| 348 | |
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| 349 | /* Set clock divider. */ |
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| 350 | BCM2835_REG(BCM2835_I2C_DIV) = divider; |
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| 351 | |
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| 352 | bus->input_clock = clock_rate; |
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| 353 | |
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| 354 | return 0; |
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| 355 | } |
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| 356 | |
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| 357 | static void rpi_i2c_destroy(i2c_bus *base) |
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| 358 | { |
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| 359 | rpi_i2c_bus *bus = (rpi_i2c_bus *) base; |
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| 360 | |
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| 361 | i2c_bus_destroy_and_free(&bus->base); |
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| 362 | } |
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| 363 | |
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| 364 | int rpi_i2c_register_bus( |
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| 365 | const char *bus_path, |
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| 366 | uint32_t bus_clock |
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| 367 | ) { |
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| 368 | #if I2C_IO_MODE == 1 |
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| 369 | rtems_status_code sc; |
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| 370 | #endif |
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| 371 | rpi_i2c_bus *bus; |
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| 372 | int rv; |
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| 373 | |
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| 374 | bus = (rpi_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus)); |
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| 375 | |
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| 376 | if ( bus == NULL ) { |
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| 377 | return -1; |
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| 378 | } |
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| 379 | |
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| 380 | /* Enable the I2C BSC interface. */ |
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| 381 | BCM2835_REG(BCM2835_I2C_C) |= (1 << 15); |
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| 382 | |
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| 383 | /* If the access to the bus is configured to be interrupt-driven. */ |
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| 384 | #if I2C_IO_MODE == 1 |
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| 385 | bus->task_id = rtems_task_self(); |
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| 386 | |
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| 387 | sc = rtems_interrupt_handler_install( |
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| 388 | BCM2835_IRQ_ID_I2C, |
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| 389 | NULL, |
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| 390 | RTEMS_INTERRUPT_UNIQUE, |
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| 391 | (rtems_interrupt_handler) i2c_handler, |
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| 392 | bus |
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| 393 | ); |
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| 394 | |
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| 395 | if ( sc != RTEMS_SUCCESSFUL ) { |
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| 396 | return -EIO; |
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| 397 | } |
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| 398 | #endif |
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| 399 | |
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| 400 | rv = rpi_i2c_set_clock(&bus->base, bus_clock); |
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| 401 | |
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| 402 | if ( rv < 0 ) { |
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| 403 | (*bus->base.destroy)(&bus->base); |
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| 404 | |
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| 405 | return -1; |
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| 406 | } |
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| 407 | |
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| 408 | bus->base.transfer = rpi_i2c_transfer; |
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| 409 | bus->base.set_clock = rpi_i2c_set_clock; |
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| 410 | bus->base.destroy = rpi_i2c_destroy; |
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| 411 | bus->base.functionality = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; |
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| 412 | |
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| 413 | return i2c_bus_register(&bus->base, bus_path); |
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| 414 | } |
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| 415 | |
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| 416 | void rpi_i2c_init(void) |
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| 417 | { |
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| 418 | /* Enable the I2C interface on the Raspberry Pi. */ |
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| 419 | rtems_gpio_initialize(); |
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| 420 | |
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| 421 | assert ( rpi_gpio_select_i2c() == RTEMS_SUCCESSFUL ); |
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| 422 | } |
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