1 | /*--------------------------------------------------------------------------------- |
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2 | |
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3 | ARM7 realtime clock |
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4 | |
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5 | Copyright (C) 2005 |
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6 | Michael Noland (joat) |
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7 | Jason Rogers (dovoto) |
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8 | Dave Murphy (WinterMute) |
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9 | |
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10 | This software is provided 'as-is', without any express or implied |
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11 | warranty. In no event will the authors be held liable for any |
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12 | damages arising from the use of this software. |
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13 | |
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14 | Permission is granted to anyone to use this software for any |
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15 | purpose, including commercial applications, and to alter it and |
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16 | redistribute it freely, subject to the following restrictions: |
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17 | |
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18 | 1. The origin of this software must not be misrepresented; you |
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19 | must not claim that you wrote the original software. If you use |
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20 | this software in a product, an acknowledgment in the product |
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21 | documentation would be appreciated but is not required. |
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22 | 2. Altered source versions must be plainly marked as such, and |
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23 | must not be misrepresented as being the original software. |
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24 | 3. This notice may not be removed or altered from any source |
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25 | distribution. |
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26 | |
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27 | ---------------------------------------------------------------------------------*/ |
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28 | |
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29 | #ifndef ARM7_CLOCK_INCLUDE |
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30 | #define ARM7_CLOCK_INCLUDE |
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31 | |
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32 | |
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33 | #ifndef ARM7 |
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34 | #error The clock is only available on the ARM7 |
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35 | #endif |
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36 | |
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37 | #ifdef __cplusplus |
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38 | extern "C" { |
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39 | #endif |
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40 | |
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41 | |
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42 | #include <nds/arm7/serial.h> |
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43 | |
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44 | // RTC registers |
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45 | #define WRITE_STATUS_REG1 0x60 |
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46 | #define READ_STATUS_REG1 0x61 |
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47 | |
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48 | /* |
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49 | Status Register 1 |
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50 | 0 W Reset (0=Normal, 1=Reset) |
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51 | 1 R/W 12/24 hour mode (0=12 hour, 1=24 hour) |
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52 | 2-3 R/W General purpose bits |
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53 | 4 R Interrupt 1 Flag (1=Yes) ;auto-cleared on read |
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54 | 5 R Interrupt 2 Flag (1=Yes) ;auto-cleared on read |
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55 | 6 R Power Low Flag (0=Normal, 1=Power is/was low) ;auto-cleared on read |
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56 | 7 R Power Off Flag (0=Normal, 1=Power was off) ;auto-cleared on read |
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57 | Power off indicates that the battery was removed or fully discharged, |
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58 | all registers are reset to 00h (or 01h), and must be re-initialized. |
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59 | */ |
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60 | #define STATUS_POC (1<<7) // read-only, cleared by reading (1 if just powered on) |
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61 | #define STATUS_BLD (1<<6) // read-only, cleared by reading (1 if power dropped below the safety threshold) |
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62 | #define STATUS_INT2 (1<<5) // read-only, INT2 has occured |
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63 | #define STATUS_INT1 (1<<4) // read-only, INT1 has occured |
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64 | #define STATUS_SC1 (1<<3) // R/W scratch bit |
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65 | #define STATUS_SC0 (1<<2) // R/W scratch bit |
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66 | #define STATUS_24HRS (1<<1) // 24 hour mode when 1, 12 hour mode when 0 |
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67 | #define STATUS_RESET (1<<0) // write-only, reset when 1 written |
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68 | |
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69 | #define WRITE_STATUS_REG2 0x62 |
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70 | #define READ_STATUS_REG2 0x63 |
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71 | /* |
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72 | Status Register 2 |
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73 | 0-3 R/W INT1 Mode/Enable |
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74 | 0000b Disable |
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75 | 0x01b Selected Frequency steady interrupt |
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76 | 0x10b Per-minute edge interrupt |
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77 | 0011b Per-minute steady interrupt 1 (duty 30.0 secomds) |
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78 | 0100b Alarm 1 interrupt |
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79 | 0111b Per-minute steady interrupt 2 (duty 0.0079 secomds) |
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80 | 1xxxb 32kHz output |
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81 | 4-5 R/W General purpose bits |
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82 | 6 R/W INT2 Enable |
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83 | 0b Disable |
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84 | 1b Alarm 2 interrupt |
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85 | 7 R/W Test Mode (0=Normal, 1=Test, don't use) (cleared on Reset) |
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86 | */ |
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87 | #define STATUS_TEST (1<<7) // |
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88 | #define STATUS_INT2AE (1<<6) // |
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89 | #define STATUS_SC3 (1<<5) // R/W scratch bit |
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90 | #define STATUS_SC2 (1<<4) // R/W scratch bit |
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91 | |
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92 | #define STATUS_32kE (1<<3) // Interrupt mode bits |
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93 | #define STATUS_INT1AE (1<<2) // |
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94 | #define STATUS_INT1ME (1<<1) // |
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95 | #define STATUS_INT1FE (1<<0) // |
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96 | |
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97 | // full 7 bytes for time and date |
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98 | #define WRITE_TIME_AND_DATE 0x64 |
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99 | #define READ_TIME_AND_DATE 0x65 |
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100 | |
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101 | // last 3 bytes of current time |
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102 | #define WRITE_TIME 0x66 |
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103 | #define READ_TIME 0x67 |
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104 | |
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105 | #define WRITE_INT_REG1 0x68 |
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106 | #define READ_INT_REG1 0x69 |
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107 | |
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108 | #define READ_INT_REG2 0x6A |
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109 | #define WRITE_INT_REG2 0x6B |
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110 | |
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111 | #define READ_CLOCK_ADJUST_REG 0x6C |
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112 | #define WRITE_CLOCK_ADJUST_REG 0x6D |
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113 | // clock-adjustment register |
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114 | |
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115 | #define READ_FREE_REG 0x6E |
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116 | #define WRITE_FREE_REG 0x6F |
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117 | |
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118 | |
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119 | void rtcReset(void); |
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120 | void rtcTransaction(uint8 * command, uint32 commandLength, uint8 * result, uint32 resultLength); |
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121 | |
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122 | void rtcGetTime(uint8 * time); |
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123 | void rtcSetTime(uint8 * time); |
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124 | |
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125 | void rtcGetTimeAndDate(uint8 * time); |
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126 | void rtcSetTimeAndDate(uint8 * time); |
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127 | |
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128 | void rtcGetData(uint8 * data, uint32 size); |
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129 | |
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130 | void BCDToInteger(uint8 * data, uint32 length); |
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131 | void integerToBCD(uint8 * data, uint32 length); |
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132 | |
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133 | void initClockIRQ(void); |
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134 | |
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135 | #ifdef __cplusplus |
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136 | } |
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137 | #endif |
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138 | |
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139 | #endif |
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140 | |
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