1 | /* |
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2 | io_efa2.c by CyteX |
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3 | |
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4 | Based on io_mpfc.c by chishm (Michael Chisholm) |
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5 | |
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6 | Hardware Routines for reading the NAND flash located on |
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7 | EFA2 flash carts |
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8 | |
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9 | This software is completely free. No warranty is provided. |
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10 | If you use it, please give me credit and email me about your |
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11 | project at cytex <at> gmx <dot> de and do not forget to also |
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12 | drop chishm <at> hotmail <dot> com a line |
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13 | |
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14 | Use with permission by Michael "Chishm" Chisholm |
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15 | */ |
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16 | |
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17 | #include "io_efa2.h" |
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18 | |
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19 | // |
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20 | // EFA2 register addresses |
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21 | // |
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22 | |
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23 | // RTC registers |
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24 | #define REG_RTC_CLK (*(vu16*)0x080000c4) |
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25 | #define REG_RTC_EN (*(vu16*)0x080000c8) |
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26 | |
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27 | // "Magic" registers used for unlock/lock sequences |
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28 | #define REG_EFA2_MAGIC_A (*(vu16*)0x09fe0000) |
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29 | #define REG_EFA2_MAGIC_B (*(vu16*)0x08000000) |
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30 | #define REG_EFA2_MAGIC_C (*(vu16*)0x08020000) |
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31 | #define REG_EFA2_MAGIC_D (*(vu16*)0x08040000) |
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32 | #define REG_EFA2_MAGIC_E (*(vu16*)0x09fc0000) |
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33 | |
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34 | // NAND flash lock/unlock register |
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35 | #define REG_EFA2_NAND_LOCK (*(vu16*)0x09c40000) |
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36 | // NAND flash enable register |
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37 | #define REG_EFA2_NAND_EN (*(vu16*)0x09400000) |
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38 | // NAND flash command write register |
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39 | #define REG_EFA2_NAND_CMD (*(vu8*)0x09ffffe2) |
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40 | // NAND flash address/data write register |
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41 | #define REG_EFA2_NAND_WR (*(vu8*)0x09ffffe0) |
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42 | // NAND flash data read register |
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43 | #define REG_EFA2_NAND_RD (*(vu8*)0x09ffc000) |
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44 | |
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45 | // ID of Samsung K9K1G NAND flash chip |
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46 | #define EFA2_NAND_ID 0xEC79A5C0 |
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47 | |
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48 | // first sector of udisk |
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49 | #define EFA2_UDSK_START 0x40 |
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50 | |
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51 | // |
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52 | // EFA2 access functions |
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53 | // |
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54 | |
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55 | // deactivate RTC ports |
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56 | static inline void _EFA2_rtc_deactivate(void) { |
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57 | REG_RTC_EN = 0; |
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58 | } |
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59 | |
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60 | // unlock register access |
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61 | static void _EFA2_reg_unlock(void) { |
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62 | REG_EFA2_MAGIC_A = 0x0d200; |
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63 | REG_EFA2_MAGIC_B = 0x01500; |
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64 | REG_EFA2_MAGIC_C = 0x0d200; |
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65 | REG_EFA2_MAGIC_D = 0x01500; |
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66 | } |
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67 | |
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68 | // finish/lock register access |
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69 | static inline void _EFA2_reg_lock(void) { |
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70 | REG_EFA2_MAGIC_E = 0x1500; |
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71 | } |
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72 | |
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73 | // global reset/init/enable/unlock ? |
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74 | static void _EFA2_global_unlock(void) { |
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75 | _EFA2_reg_unlock(); |
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76 | *(vu16*)0x09880000 = 0x08000; |
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77 | _EFA2_reg_lock(); |
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78 | } |
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79 | |
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80 | // global lock, stealth mode |
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81 | /*static void _EFA2_global_lock(void) { |
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82 | // quite sure there is such a sequence, but haven't had |
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83 | // a look for it upto now |
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84 | }*/ |
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85 | |
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86 | // unlock NAND Flash |
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87 | static void _EFA2_nand_unlock(void) { |
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88 | _EFA2_reg_unlock(); |
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89 | REG_EFA2_NAND_LOCK = 0x01500; |
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90 | _EFA2_reg_lock(); |
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91 | } |
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92 | |
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93 | // lock NAND Flash |
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94 | static void _EFA2_nand_lock(void) { |
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95 | _EFA2_reg_unlock(); |
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96 | REG_EFA2_NAND_LOCK = 0x0d200; |
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97 | _EFA2_reg_lock(); |
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98 | } |
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99 | |
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100 | // |
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101 | // Set NAND Flash chip enable and write protection bits ? |
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102 | // |
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103 | // val | ~CE | ~WP | |
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104 | // -----+-----+-----+ |
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105 | // 0 | 0 | 0 | |
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106 | // 1 | 1 | 0 | |
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107 | // 3 | 1 | 1 | |
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108 | // -----+-----+-----+ |
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109 | // |
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110 | static void _EFA2_nand_enable(u16 val) { |
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111 | _EFA2_reg_unlock(); |
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112 | REG_EFA2_NAND_EN = val; |
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113 | _EFA2_reg_lock(); |
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114 | } |
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115 | |
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116 | // |
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117 | // Perform NAND reset |
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118 | // NAND has to be unlocked and enabled when called |
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119 | // |
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120 | static inline void _EFA2_nand_reset(void) { |
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121 | REG_EFA2_NAND_CMD = 0xff; // write reset command |
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122 | } |
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123 | |
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124 | // |
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125 | // Read out NAND ID information, could be used for card detection |
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126 | // |
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127 | // | EFA2 1GBit | |
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128 | // ------------------+------------+ |
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129 | // maker code | 0xEC | |
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130 | // device code | 0x79 | |
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131 | // don't care | 0xA5 | |
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132 | // multi plane code | 0xC0 | |
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133 | // ------------------+------------+ |
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134 | // |
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135 | static u32 _EFA2_nand_id(void) { |
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136 | u8 byte; |
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137 | u32 id; |
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138 | |
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139 | _EFA2_nand_unlock(); |
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140 | _EFA2_nand_enable(1); |
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141 | |
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142 | REG_EFA2_NAND_CMD = 0x90; // write id command |
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143 | REG_EFA2_NAND_WR = 0x00; // (dummy) address cycle |
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144 | byte = REG_EFA2_NAND_RD; // read maker code |
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145 | id = byte; |
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146 | byte = REG_EFA2_NAND_RD; // read device code |
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147 | id = (id << 8) | byte; |
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148 | byte = REG_EFA2_NAND_RD; // read don't care |
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149 | id = (id << 8) | byte; |
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150 | byte = REG_EFA2_NAND_RD; // read multi plane code |
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151 | id = (id << 8) | byte; |
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152 | |
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153 | _EFA2_nand_enable(0); |
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154 | _EFA2_nand_lock(); |
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155 | return (id); |
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156 | } |
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157 | |
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158 | // |
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159 | // Start of gba_nds_fat block device description |
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160 | // |
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161 | |
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162 | /*----------------------------------------------------------------- |
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163 | EFA2_clearStatus |
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164 | Reads and checks NAND status information |
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165 | bool return OUT: true if NAND is idle |
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166 | -----------------------------------------------------------------*/ |
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167 | static bool _EFA2_clearStatus (void) |
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168 | { |
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169 | // tbd: currently there is no write support, so always return |
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170 | // true, there is no possibility for pending operations |
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171 | return true; |
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172 | } |
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173 | |
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174 | /*----------------------------------------------------------------- |
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175 | EFA2_isInserted |
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176 | Checks to see if the NAND chip used by the EFA2 is present |
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177 | bool return OUT: true if the correct NAND chip is found |
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178 | -----------------------------------------------------------------*/ |
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179 | static bool _EFA2_isInserted (void) |
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180 | { |
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181 | _EFA2_clearStatus(); |
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182 | return (_EFA2_nand_id() == EFA2_NAND_ID); |
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183 | } |
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184 | |
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185 | /*----------------------------------------------------------------- |
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186 | EFA2_readSectors |
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187 | Read "numSecs" 512 byte sectors starting from "sector" into "buffer" |
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188 | No error correction, no use of spare cells, no use of R/~B signal |
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189 | u32 sector IN: number of first 512 byte sector to be read |
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190 | u32 numSecs IN: number of 512 byte sectors to read, |
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191 | void* buffer OUT: pointer to 512 byte buffer to store data in |
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192 | bool return OUT: true if successful |
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193 | -----------------------------------------------------------------*/ |
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194 | static bool _EFA2_readSectors (u32 sector, u32 numSecs, void* buffer) |
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195 | { |
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196 | int i; |
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197 | |
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198 | #ifndef _IO_ALLOW_UNALIGNED |
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199 | u8 byte; |
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200 | u16 word; |
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201 | #endif |
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202 | |
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203 | // NAND page 0x40 (EFA2_UDSK_START) contains the MBR of the |
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204 | // udisk and thus is sector 0. The original EFA2 firmware |
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205 | // does never look at this, it only watches page 0x60, which |
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206 | // contains the boot block of the FAT16 partition. That is |
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207 | // fixed, so the EFA2 udisk must not be reformated, else |
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208 | // the ARK Octopus and also the original Firmware won't be |
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209 | // able to access the udisk anymore and I have to write a |
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210 | // recovery tool. |
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211 | u32 page = EFA2_UDSK_START + sector; |
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212 | |
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213 | // future enhancement: wait for possible write operations to |
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214 | // be finisched |
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215 | if (!_EFA2_clearStatus()) return false; |
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216 | |
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217 | _EFA2_nand_unlock(); |
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218 | _EFA2_nand_enable(1); |
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219 | _EFA2_nand_reset(); |
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220 | |
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221 | // set NAND to READ1 operation mode and transfer page address |
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222 | REG_EFA2_NAND_CMD = 0x00; // write READ1 command |
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223 | REG_EFA2_NAND_WR = 0x00; // write address [7:0] |
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224 | REG_EFA2_NAND_WR = (page ) & 0xff; // write address [15:8] |
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225 | REG_EFA2_NAND_WR = (page >> 8 ) & 0xff; // write address[23:16] |
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226 | REG_EFA2_NAND_WR = (page >> 16) & 0xff; // write address[26:24] |
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227 | |
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228 | // Due to a bug in EFA2 design there is need to waste some cycles |
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229 | // "by hand" instead the possibility to check the R/~B port of |
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230 | // the NAND flash via a register. The RTC deactivation is only |
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231 | // there to make sure the loop won't be optimized by the compiler |
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232 | for (i=0 ; i < 3 ; i++) _EFA2_rtc_deactivate(); |
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233 | |
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234 | while (numSecs--) |
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235 | { |
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236 | // read page data |
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237 | #ifdef _IO_ALLOW_UNALIGNED |
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238 | // slow byte access to RAM, but works in principle |
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239 | for (i=0 ; i < 512 ; i++) |
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240 | ((u8*)buffer)[i] = REG_EFA2_NAND_RD; |
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241 | #else |
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242 | // a bit faster, but DMA is not possible |
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243 | for (i=0 ; i < 256 ; i++) { |
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244 | byte = REG_EFA2_NAND_RD; // read lo-byte |
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245 | word = byte; |
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246 | byte = REG_EFA2_NAND_RD; // read hi-byte |
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247 | word = word | (byte << 8); |
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248 | ((u16*)buffer)[i] = word; |
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249 | } |
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250 | #endif |
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251 | } |
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252 | |
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253 | _EFA2_nand_enable(0); |
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254 | _EFA2_nand_lock(); |
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255 | return true; |
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256 | } |
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257 | |
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258 | |
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259 | /*----------------------------------------------------------------- |
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260 | EFA2_writeSectors |
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261 | Write "numSecs" 512 byte sectors starting at "sector" from "buffer" |
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262 | u32 sector IN: address of 512 byte sector on card to write |
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263 | u32 numSecs IN: number of 512 byte sectors to write |
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264 | 1 to 256 sectors can be written, 0 = 256 |
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265 | void* buffer IN: pointer to 512 byte buffer to read data from |
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266 | bool return OUT: true if successful |
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267 | -----------------------------------------------------------------*/ |
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268 | static bool _EFA2_writeSectors (u32 sector, u8 numSecs, void* buffer) |
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269 | { |
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270 | // Upto now I focused on reading NAND, write operations |
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271 | // will follow |
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272 | return false; |
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273 | } |
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274 | |
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275 | /*----------------------------------------------------------------- |
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276 | EFA2_shutdown |
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277 | unload the EFA2 interface |
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278 | -----------------------------------------------------------------*/ |
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279 | static bool _EFA2_shutdown(void) |
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280 | { |
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281 | return _EFA2_clearStatus(); |
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282 | } |
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283 | |
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284 | /*----------------------------------------------------------------- |
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285 | EFA2_startUp |
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286 | initializes the EFA2 card, returns true if successful, |
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287 | otherwise returns false |
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288 | -----------------------------------------------------------------*/ |
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289 | static bool _EFA2_startUp(void) |
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290 | { |
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291 | _EFA2_global_unlock(); |
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292 | return (_EFA2_nand_id() == EFA2_NAND_ID); |
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293 | } |
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294 | |
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295 | /*----------------------------------------------------------------- |
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296 | the actual interface structure |
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297 | -----------------------------------------------------------------*/ |
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298 | const IO_INTERFACE _io_efa2 = { |
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299 | DEVICE_TYPE_EFA2, |
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300 | FEATURE_MEDIUM_CANREAD | FEATURE_SLOT_GBA, |
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301 | (FN_MEDIUM_STARTUP)&_EFA2_startUp, |
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302 | (FN_MEDIUM_ISINSERTED)&_EFA2_isInserted, |
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303 | (FN_MEDIUM_READSECTORS)&_EFA2_readSectors, |
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304 | (FN_MEDIUM_WRITESECTORS)&_EFA2_writeSectors, |
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305 | (FN_MEDIUM_CLEARSTATUS)&_EFA2_clearStatus, |
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306 | (FN_MEDIUM_SHUTDOWN)&_EFA2_shutdown |
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307 | }; |
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