1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx |
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5 | * |
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6 | * @brief Startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/start.h> |
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25 | #include <bsp/lpc32xx.h> |
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26 | #include <bsp/mmu.h> |
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27 | #include <bsp/linker-symbols.h> |
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28 | #include <bsp/uart-output-char.h> |
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29 | |
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30 | #ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE |
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31 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE |
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32 | #else |
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33 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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34 | #endif |
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35 | |
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36 | #ifdef LPC32XX_DISABLE_READ_ONLY_PROTECTION |
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37 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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38 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_WRITE_CACHED |
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39 | #else |
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40 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_ONLY_CACHED |
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41 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_ONLY_CACHED |
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42 | #endif |
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43 | |
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44 | LINKER_SYMBOL(lpc32xx_translation_table_base); |
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45 | |
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46 | static BSP_START_TEXT_SECTION void clear_bss(void) |
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47 | { |
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48 | const int *end = (const int *) bsp_section_bss_end; |
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49 | int *out = (int *) bsp_section_bss_begin; |
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50 | |
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51 | /* Clear BSS */ |
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52 | while (out != end) { |
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53 | *out = 0; |
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54 | ++out; |
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55 | } |
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56 | } |
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57 | |
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58 | #ifndef LPC32XX_DISABLE_MMU |
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59 | typedef struct { |
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60 | uint32_t begin; |
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61 | uint32_t end; |
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62 | uint32_t flags; |
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63 | } lpc32xx_mmu_config; |
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64 | |
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65 | static const BSP_START_DATA_SECTION lpc32xx_mmu_config |
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66 | lpc32xx_mmu_config_table [] = { |
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67 | { |
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68 | .begin = (uint32_t) bsp_section_fast_text_begin, |
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69 | .end = (uint32_t) bsp_section_fast_text_end, |
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70 | .flags = LPC32XX_MMU_CODE |
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71 | }, { |
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72 | .begin = (uint32_t) bsp_section_fast_data_begin, |
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73 | .end = (uint32_t) bsp_section_fast_data_end, |
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74 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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75 | #ifdef LPC32XX_SCRATCH_AREA_SIZE |
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76 | }, { |
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77 | .begin = (uint32_t) &lpc32xx_scratch_area [0], |
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78 | .end = (uint32_t) &lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE], |
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79 | .flags = LPC32XX_MMU_READ_ONLY_DATA |
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80 | #endif |
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81 | }, { |
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82 | .begin = (uint32_t) bsp_section_start_begin, |
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83 | .end = (uint32_t) bsp_section_start_end, |
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84 | .flags = LPC32XX_MMU_CODE |
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85 | }, { |
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86 | .begin = (uint32_t) bsp_section_vector_begin, |
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87 | .end = (uint32_t) bsp_section_vector_end, |
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88 | .flags = LPC32XX_MMU_READ_WRITE_CACHED |
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89 | }, { |
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90 | .begin = (uint32_t) bsp_section_text_begin, |
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91 | .end = (uint32_t) bsp_section_text_end, |
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92 | .flags = LPC32XX_MMU_CODE |
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93 | }, { |
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94 | .begin = (uint32_t) bsp_section_rodata_begin, |
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95 | .end = (uint32_t) bsp_section_rodata_end, |
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96 | .flags = LPC32XX_MMU_READ_ONLY_DATA |
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97 | }, { |
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98 | .begin = (uint32_t) bsp_section_data_begin, |
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99 | .end = (uint32_t) bsp_section_data_end, |
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100 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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101 | }, { |
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102 | .begin = (uint32_t) bsp_section_bss_begin, |
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103 | .end = (uint32_t) bsp_section_bss_end, |
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104 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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105 | }, { |
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106 | .begin = (uint32_t) bsp_section_work_begin, |
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107 | .end = (uint32_t) bsp_section_work_end, |
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108 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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109 | }, { |
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110 | .begin = (uint32_t) bsp_section_stack_begin, |
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111 | .end = (uint32_t) bsp_section_stack_end, |
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112 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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113 | }, { |
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114 | .begin = 0x0U, |
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115 | .end = 0x100000U, |
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116 | .flags = LPC32XX_MMU_READ_ONLY_CACHED |
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117 | }, { |
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118 | .begin = 0x20000000U, |
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119 | .end = 0x200c0000U, |
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120 | .flags = LPC32XX_MMU_READ_WRITE |
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121 | }, { |
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122 | .begin = 0x30000000U, |
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123 | .end = 0x32000000U, |
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124 | .flags = LPC32XX_MMU_READ_WRITE |
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125 | }, { |
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126 | .begin = 0x40000000U, |
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127 | .end = 0x40100000U, |
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128 | .flags = LPC32XX_MMU_READ_WRITE |
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129 | }, { |
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130 | .begin = (uint32_t) lpc32xx_magic_zero_begin, |
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131 | .end = (uint32_t) lpc32xx_magic_zero_end, |
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132 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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133 | } |
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134 | }; |
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135 | |
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136 | static BSP_START_TEXT_SECTION void set_translation_table_entries( |
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137 | uint32_t *ttb, |
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138 | const lpc32xx_mmu_config *config |
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139 | ) |
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140 | { |
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141 | uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); |
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142 | uint32_t iend = |
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143 | ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); |
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144 | |
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145 | if (config->begin != config->end) { |
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146 | while (i < iend) { |
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147 | ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; |
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148 | ++i; |
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149 | } |
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150 | } |
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151 | } |
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152 | |
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153 | static BSP_START_TEXT_SECTION void |
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154 | setup_translation_table_and_enable_mmu(uint32_t ctrl) |
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155 | { |
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156 | uint32_t const dac = |
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157 | ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT); |
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158 | uint32_t *const ttb = (uint32_t *) lpc32xx_translation_table_base; |
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159 | size_t const config_entry_count = |
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160 | sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]); |
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161 | size_t i = 0; |
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162 | |
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163 | arm_cp15_set_domain_access_control(dac); |
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164 | arm_cp15_set_translation_table_base(ttb); |
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165 | |
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166 | /* Initialize translation table with invalid entries */ |
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167 | for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { |
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168 | ttb [i] = 0; |
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169 | } |
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170 | |
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171 | for (i = 0; i < config_entry_count; ++i) { |
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172 | set_translation_table_entries(ttb, &lpc32xx_mmu_config_table [i]); |
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173 | } |
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174 | |
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175 | /* Enable MMU and cache */ |
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176 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
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177 | arm_cp15_set_control(ctrl); |
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178 | } |
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179 | #endif |
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180 | |
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181 | static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void) |
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182 | { |
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183 | uint32_t ctrl = 0; |
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184 | |
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185 | /* Disable MMU and cache, basic settings */ |
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186 | ctrl = arm_cp15_get_control(); |
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187 | ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C |
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188 | | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M); |
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189 | ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A; |
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190 | arm_cp15_set_control(ctrl); |
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191 | |
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192 | arm_cp15_cache_invalidate(); |
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193 | arm_cp15_tlb_invalidate(); |
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194 | |
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195 | #ifndef LPC32XX_DISABLE_MMU |
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196 | setup_translation_table_and_enable_mmu(ctrl); |
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197 | #endif |
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198 | } |
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199 | |
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200 | BSP_START_TEXT_SECTION bool lpc32xx_start_pll_setup( |
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201 | uint32_t hclkpll_ctrl, |
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202 | uint32_t hclkdiv_ctrl, |
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203 | bool force |
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204 | ) |
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205 | { |
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206 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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207 | bool settings_ok = |
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208 | ((LPC32XX_HCLKPLL_CTRL ^ hclkpll_ctrl) & BSP_MSK32(1, 16)) == 0 |
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209 | && ((LPC32XX_HCLKDIV_CTRL ^ hclkdiv_ctrl) & BSP_MSK32(0, 8)) == 0; |
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210 | |
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211 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0 || (!settings_ok && force)) { |
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212 | /* Disable HCLK PLL output */ |
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213 | LPC32XX_PWR_CTRL = pwr_ctrl & ~PWR_NORMAL_RUN_MODE; |
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214 | |
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215 | /* Configure HCLK PLL */ |
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216 | LPC32XX_HCLKPLL_CTRL = hclkpll_ctrl; |
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217 | while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) { |
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218 | /* Wait */ |
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219 | } |
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220 | |
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221 | /* Setup HCLK divider */ |
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222 | LPC32XX_HCLKDIV_CTRL = hclkdiv_ctrl; |
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223 | |
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224 | /* Enable HCLK PLL output */ |
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225 | LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE; |
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226 | } |
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227 | |
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228 | return settings_ok; |
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229 | } |
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230 | |
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231 | #if LPC32XX_OSCILLATOR_MAIN != 13000000U |
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232 | #error "unexpected main oscillator frequency" |
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233 | #endif |
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234 | |
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235 | static BSP_START_TEXT_SECTION void setup_pll(void) |
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236 | { |
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237 | uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL_INIT_VALUE; |
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238 | uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL_INIT_VALUE; |
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239 | |
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240 | lpc32xx_start_pll_setup(hclkpll_ctrl, hclkdiv_ctrl, false); |
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241 | } |
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242 | |
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243 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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244 | { |
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245 | setup_pll(); |
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246 | setup_mmu_and_cache(); |
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247 | } |
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248 | |
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249 | static BSP_START_TEXT_SECTION void stop_dma_activities(void) |
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250 | { |
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251 | #ifdef LPC32XX_STOP_GPDMA |
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252 | LPC32XX_DO_STOP_GPDMA; |
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253 | #endif |
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254 | |
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255 | #ifdef LPC32XX_STOP_ETHERNET |
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256 | LPC32XX_DO_STOP_ETHERNET; |
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257 | #endif |
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258 | |
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259 | #ifdef LPC32XX_STOP_USB |
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260 | LPC32XX_DO_STOP_USB; |
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261 | #endif |
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262 | } |
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263 | |
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264 | static BSP_START_TEXT_SECTION void setup_uarts(void) |
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265 | { |
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266 | LPC32XX_UART_CTRL = 0x0; |
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267 | LPC32XX_UART_LOOP = 0x0; |
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268 | |
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269 | #ifdef LPC32XX_UART_5_BAUD |
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270 | LPC32XX_UARTCLK_CTRL |= 1U << 2; |
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271 | LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; |
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272 | LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 8, 9); |
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273 | BSP_CONSOLE_UART_INIT(0x01); |
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274 | #endif |
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275 | } |
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276 | |
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277 | static BSP_START_TEXT_SECTION void setup_timer(void) |
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278 | { |
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279 | volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; |
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280 | |
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281 | LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3); |
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282 | |
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283 | timer->tcr = LPC_TIMER_TCR_RST; |
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284 | timer->ctcr = 0x0; |
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285 | timer->pr = 0x0; |
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286 | timer->ir = 0xff; |
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287 | timer->mcr = 0x0; |
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288 | timer->ccr = 0x0; |
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289 | timer->tcr = LPC_TIMER_TCR_EN; |
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290 | } |
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291 | |
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292 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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293 | { |
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294 | stop_dma_activities(); |
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295 | setup_uarts(); |
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296 | setup_timer(); |
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297 | |
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298 | /* Copy .text section */ |
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299 | arm_cp15_instruction_cache_invalidate(); |
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300 | bsp_start_memcpy( |
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301 | (int *) bsp_section_text_begin, |
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302 | (const int *) bsp_section_text_load_begin, |
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303 | (size_t) bsp_section_text_size |
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304 | ); |
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305 | |
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306 | /* Copy .rodata section */ |
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307 | arm_cp15_instruction_cache_invalidate(); |
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308 | bsp_start_memcpy( |
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309 | (int *) bsp_section_rodata_begin, |
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310 | (const int *) bsp_section_rodata_load_begin, |
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311 | (size_t) bsp_section_rodata_size |
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312 | ); |
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313 | |
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314 | /* Copy .data section */ |
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315 | arm_cp15_instruction_cache_invalidate(); |
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316 | bsp_start_memcpy( |
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317 | (int *) bsp_section_data_begin, |
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318 | (const int *) bsp_section_data_load_begin, |
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319 | (size_t) bsp_section_data_size |
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320 | ); |
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321 | |
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322 | /* Copy .fast_text section */ |
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323 | arm_cp15_instruction_cache_invalidate(); |
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324 | bsp_start_memcpy( |
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325 | (int *) bsp_section_fast_text_begin, |
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326 | (const int *) bsp_section_fast_text_load_begin, |
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327 | (size_t) bsp_section_fast_text_size |
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328 | ); |
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329 | |
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330 | /* Copy .fast_data section */ |
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331 | arm_cp15_instruction_cache_invalidate(); |
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332 | bsp_start_memcpy( |
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333 | (int *) bsp_section_fast_data_begin, |
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334 | (const int *) bsp_section_fast_data_load_begin, |
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335 | (size_t) bsp_section_fast_data_size |
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336 | ); |
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337 | |
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338 | /* Clear .bss section */ |
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339 | clear_bss(); |
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340 | |
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341 | /* At this point we can use objects outside the .start section */ |
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342 | } |
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