1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_lpc32xx |
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5 | * |
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6 | * @brief Startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/start.h> |
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25 | #include <bsp/lpc32xx.h> |
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26 | #include <bsp/mmu.h> |
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27 | #include <bsp/arm-cp15-start.h> |
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28 | #include <bsp/linker-symbols.h> |
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29 | #include <bsp/uart-output-char.h> |
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30 | |
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31 | #ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE |
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32 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE |
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33 | #else |
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34 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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35 | #endif |
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36 | |
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37 | #ifdef LPC32XX_DISABLE_READ_ONLY_PROTECTION |
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38 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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39 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_WRITE_CACHED |
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40 | #else |
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41 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_ONLY_CACHED |
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42 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_ONLY_CACHED |
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43 | #endif |
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44 | |
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45 | #ifndef LPC32XX_DISABLE_MMU |
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46 | static const BSP_START_DATA_SECTION arm_cp15_start_section_config |
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47 | lpc32xx_mmu_config_table [] = { |
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48 | { |
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49 | .begin = (uint32_t) bsp_section_fast_text_begin, |
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50 | .end = (uint32_t) bsp_section_fast_text_end, |
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51 | .flags = LPC32XX_MMU_CODE |
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52 | }, { |
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53 | .begin = (uint32_t) bsp_section_fast_data_begin, |
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54 | .end = (uint32_t) bsp_section_fast_data_end, |
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55 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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56 | #ifdef LPC32XX_SCRATCH_AREA_SIZE |
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57 | }, { |
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58 | .begin = (uint32_t) &lpc32xx_scratch_area [0], |
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59 | .end = (uint32_t) &lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE], |
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60 | .flags = LPC32XX_MMU_READ_ONLY_DATA |
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61 | #endif |
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62 | }, { |
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63 | .begin = (uint32_t) bsp_section_start_begin, |
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64 | .end = (uint32_t) bsp_section_start_end, |
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65 | .flags = LPC32XX_MMU_CODE |
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66 | }, { |
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67 | .begin = (uint32_t) bsp_section_vector_begin, |
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68 | .end = (uint32_t) bsp_section_vector_end, |
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69 | .flags = LPC32XX_MMU_READ_WRITE_CACHED |
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70 | }, { |
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71 | .begin = (uint32_t) bsp_section_text_begin, |
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72 | .end = (uint32_t) bsp_section_text_end, |
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73 | .flags = LPC32XX_MMU_CODE |
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74 | }, { |
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75 | .begin = (uint32_t) bsp_section_rodata_begin, |
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76 | .end = (uint32_t) bsp_section_rodata_end, |
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77 | .flags = LPC32XX_MMU_READ_ONLY_DATA |
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78 | }, { |
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79 | .begin = (uint32_t) bsp_section_data_begin, |
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80 | .end = (uint32_t) bsp_section_data_end, |
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81 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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82 | }, { |
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83 | .begin = (uint32_t) bsp_section_bss_begin, |
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84 | .end = (uint32_t) bsp_section_bss_end, |
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85 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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86 | }, { |
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87 | .begin = (uint32_t) bsp_section_work_begin, |
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88 | .end = (uint32_t) bsp_section_work_end, |
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89 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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90 | }, { |
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91 | .begin = (uint32_t) bsp_section_stack_begin, |
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92 | .end = (uint32_t) bsp_section_stack_end, |
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93 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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94 | }, { |
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95 | .begin = 0x0U, |
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96 | .end = 0x100000U, |
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97 | .flags = LPC32XX_MMU_READ_ONLY_CACHED |
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98 | }, { |
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99 | .begin = 0x20000000U, |
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100 | .end = 0x200c0000U, |
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101 | .flags = LPC32XX_MMU_READ_WRITE |
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102 | }, { |
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103 | .begin = 0x30000000U, |
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104 | .end = 0x32000000U, |
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105 | .flags = LPC32XX_MMU_READ_WRITE |
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106 | }, { |
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107 | .begin = 0x40000000U, |
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108 | .end = 0x40100000U, |
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109 | .flags = LPC32XX_MMU_READ_WRITE |
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110 | }, { |
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111 | .begin = (uint32_t) lpc32xx_magic_zero_begin, |
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112 | .end = (uint32_t) lpc32xx_magic_zero_end, |
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113 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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114 | } |
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115 | }; |
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116 | #endif |
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117 | |
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118 | static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void) |
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119 | { |
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120 | uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( |
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121 | ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C |
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122 | | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M, |
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123 | ARM_CP15_CTRL_S | ARM_CP15_CTRL_A |
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124 | ); |
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125 | |
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126 | arm_cp15_cache_invalidate(); |
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127 | |
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128 | #ifndef LPC32XX_DISABLE_MMU |
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129 | arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( |
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130 | ctrl, |
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131 | (uint32_t *) bsp_translation_table_base, |
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132 | LPC32XX_MMU_CLIENT_DOMAIN, |
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133 | &lpc32xx_mmu_config_table [0], |
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134 | RTEMS_ARRAY_SIZE(lpc32xx_mmu_config_table) |
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135 | ); |
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136 | #endif |
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137 | } |
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138 | |
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139 | BSP_START_TEXT_SECTION bool lpc32xx_start_pll_setup( |
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140 | uint32_t hclkpll_ctrl, |
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141 | uint32_t hclkdiv_ctrl, |
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142 | bool force |
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143 | ) |
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144 | { |
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145 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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146 | bool settings_ok = |
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147 | ((LPC32XX_HCLKPLL_CTRL ^ hclkpll_ctrl) & BSP_MSK32(1, 16)) == 0 |
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148 | && ((LPC32XX_HCLKDIV_CTRL ^ hclkdiv_ctrl) & BSP_MSK32(0, 8)) == 0; |
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149 | |
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150 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0 || (!settings_ok && force)) { |
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151 | /* Disable HCLK PLL output */ |
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152 | LPC32XX_PWR_CTRL = pwr_ctrl & ~PWR_NORMAL_RUN_MODE; |
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153 | |
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154 | /* Configure HCLK PLL */ |
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155 | LPC32XX_HCLKPLL_CTRL = hclkpll_ctrl; |
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156 | while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) { |
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157 | /* Wait */ |
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158 | } |
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159 | |
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160 | /* Setup HCLK divider */ |
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161 | LPC32XX_HCLKDIV_CTRL = hclkdiv_ctrl; |
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162 | |
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163 | /* Enable HCLK PLL output */ |
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164 | LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE; |
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165 | } |
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166 | |
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167 | return settings_ok; |
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168 | } |
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169 | |
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170 | #if LPC32XX_OSCILLATOR_MAIN != 13000000U |
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171 | #error "unexpected main oscillator frequency" |
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172 | #endif |
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173 | |
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174 | static BSP_START_TEXT_SECTION void setup_pll(void) |
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175 | { |
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176 | uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL_INIT_VALUE; |
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177 | uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL_INIT_VALUE; |
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178 | |
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179 | lpc32xx_start_pll_setup(hclkpll_ctrl, hclkdiv_ctrl, false); |
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180 | } |
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181 | |
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182 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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183 | { |
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184 | setup_pll(); |
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185 | } |
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186 | |
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187 | static BSP_START_TEXT_SECTION void stop_dma_activities(void) |
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188 | { |
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189 | #ifdef LPC32XX_STOP_GPDMA |
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190 | LPC32XX_DO_STOP_GPDMA; |
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191 | #endif |
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192 | |
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193 | #ifdef LPC32XX_STOP_ETHERNET |
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194 | LPC32XX_DO_STOP_ETHERNET; |
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195 | #endif |
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196 | |
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197 | #ifdef LPC32XX_STOP_USB |
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198 | LPC32XX_DO_STOP_USB; |
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199 | #endif |
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200 | } |
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201 | |
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202 | static BSP_START_TEXT_SECTION void setup_uarts(void) |
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203 | { |
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204 | LPC32XX_UART_CTRL = 0x0; |
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205 | LPC32XX_UART_LOOP = 0x0; |
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206 | |
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207 | #ifdef LPC32XX_UART_5_BAUD |
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208 | LPC32XX_UARTCLK_CTRL |= 1U << 2; |
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209 | LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; |
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210 | LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 8, 9); |
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211 | BSP_CONSOLE_UART_INIT(0x01); |
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212 | #endif |
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213 | } |
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214 | |
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215 | static BSP_START_TEXT_SECTION void setup_timer(void) |
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216 | { |
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217 | volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; |
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218 | |
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219 | LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3); |
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220 | |
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221 | timer->tcr = LPC_TIMER_TCR_RST; |
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222 | timer->ctcr = 0x0; |
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223 | timer->pr = 0x0; |
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224 | timer->ir = 0xff; |
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225 | timer->mcr = 0x0; |
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226 | timer->ccr = 0x0; |
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227 | timer->tcr = LPC_TIMER_TCR_EN; |
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228 | } |
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229 | |
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230 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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231 | { |
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232 | stop_dma_activities(); |
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233 | bsp_start_copy_sections(); |
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234 | setup_mmu_and_cache(); |
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235 | setup_uarts(); |
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236 | setup_timer(); |
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237 | bsp_start_clear_bss(); |
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238 | } |
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