1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx |
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5 | * |
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6 | * @brief Startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #include <stdbool.h> |
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23 | |
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24 | #include <bspopts.h> |
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25 | #include <bsp/start.h> |
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26 | #include <bsp/lpc32xx.h> |
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27 | #include <bsp/mmu.h> |
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28 | #include <bsp/linker-symbols.h> |
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29 | #include <bsp/uart-output-char.h> |
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30 | |
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31 | #ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE |
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32 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE |
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33 | #else |
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34 | #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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35 | #endif |
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36 | |
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37 | #ifdef LPC32XX_DISABLE_READ_ONLY_PROTECTION |
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38 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_WRITE_CACHED |
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39 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_WRITE_CACHED |
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40 | #else |
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41 | #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_ONLY_CACHED |
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42 | #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_ONLY_CACHED |
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43 | #endif |
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44 | |
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45 | LINKER_SYMBOL(lpc32xx_translation_table_base); |
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46 | |
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47 | static void BSP_START_SECTION clear_bss(void) |
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48 | { |
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49 | const int *end = (const int *) bsp_section_bss_end; |
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50 | int *out = (int *) bsp_section_bss_begin; |
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51 | |
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52 | /* Clear BSS */ |
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53 | while (out != end) { |
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54 | *out = 0; |
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55 | ++out; |
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56 | } |
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57 | } |
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58 | |
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59 | #ifndef LPC32XX_DISABLE_MMU |
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60 | typedef struct { |
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61 | uint32_t begin; |
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62 | uint32_t end; |
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63 | uint32_t flags; |
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64 | } lpc32xx_mmu_config; |
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65 | |
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66 | static const BSP_START_DATA_SECTION lpc32xx_mmu_config |
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67 | lpc32xx_mmu_config_table [] = { |
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68 | { |
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69 | .begin = (uint32_t) bsp_section_start_begin, |
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70 | .end = (uint32_t) bsp_section_start_end, |
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71 | .flags = LPC32XX_MMU_CODE |
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72 | }, { |
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73 | .begin = (uint32_t) bsp_section_vector_begin, |
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74 | .end = (uint32_t) bsp_section_vector_end, |
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75 | .flags = LPC32XX_MMU_READ_WRITE_CACHED |
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76 | }, { |
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77 | .begin = (uint32_t) bsp_section_text_begin, |
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78 | .end = (uint32_t) bsp_section_text_end, |
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79 | .flags = LPC32XX_MMU_CODE |
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80 | }, { |
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81 | .begin = (uint32_t) bsp_section_rodata_begin, |
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82 | .end = (uint32_t) bsp_section_rodata_end, |
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83 | .flags = LPC32XX_MMU_READ_ONLY_DATA |
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84 | }, { |
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85 | .begin = (uint32_t) bsp_section_data_begin, |
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86 | .end = (uint32_t) bsp_section_data_end, |
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87 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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88 | }, { |
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89 | .begin = (uint32_t) bsp_section_fast_begin, |
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90 | .end = (uint32_t) bsp_section_fast_end, |
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91 | .flags = LPC32XX_MMU_CODE |
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92 | }, { |
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93 | .begin = (uint32_t) bsp_section_bss_begin, |
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94 | .end = (uint32_t) bsp_section_bss_end, |
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95 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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96 | }, { |
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97 | .begin = (uint32_t) bsp_section_work_begin, |
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98 | .end = (uint32_t) bsp_section_work_end, |
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99 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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100 | }, { |
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101 | .begin = (uint32_t) bsp_section_stack_begin, |
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102 | .end = (uint32_t) bsp_section_stack_end, |
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103 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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104 | }, { |
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105 | .begin = 0x0U, |
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106 | .end = 0x100000U, |
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107 | .flags = LPC32XX_MMU_READ_ONLY_CACHED |
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108 | }, { |
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109 | .begin = 0x20000000U, |
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110 | .end = 0x200c0000U, |
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111 | .flags = LPC32XX_MMU_READ_WRITE |
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112 | }, { |
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113 | .begin = 0x30000000U, |
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114 | .end = 0x32000000U, |
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115 | .flags = LPC32XX_MMU_READ_WRITE |
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116 | }, { |
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117 | .begin = 0x40000000U, |
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118 | .end = 0x40100000U, |
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119 | .flags = LPC32XX_MMU_READ_WRITE |
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120 | }, { |
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121 | .begin = (uint32_t) lpc32xx_magic_zero_begin, |
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122 | .end = (uint32_t) lpc32xx_magic_zero_end, |
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123 | .flags = LPC32XX_MMU_READ_WRITE_DATA |
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124 | } |
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125 | }; |
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126 | |
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127 | static void BSP_START_SECTION set_translation_table_entries( |
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128 | uint32_t *ttb, |
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129 | const lpc32xx_mmu_config *config |
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130 | ) |
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131 | { |
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132 | uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); |
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133 | uint32_t iend = |
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134 | ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); |
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135 | |
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136 | if (config->begin != config->end) { |
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137 | while (i < iend) { |
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138 | ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; |
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139 | ++i; |
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140 | } |
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141 | } |
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142 | } |
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143 | |
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144 | static void BSP_START_SECTION |
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145 | setup_translation_table_and_enable_mmu(uint32_t ctrl) |
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146 | { |
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147 | uint32_t const dac = |
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148 | ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT); |
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149 | uint32_t *const ttb = (uint32_t *) lpc32xx_translation_table_base; |
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150 | size_t const config_entry_count = |
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151 | sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]); |
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152 | size_t i = 0; |
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153 | |
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154 | arm_cp15_set_domain_access_control(dac); |
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155 | arm_cp15_set_translation_table_base(ttb); |
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156 | |
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157 | /* Initialize translation table with invalid entries */ |
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158 | for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { |
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159 | ttb [i] = 0; |
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160 | } |
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161 | |
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162 | for (i = 0; i < config_entry_count; ++i) { |
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163 | set_translation_table_entries(ttb, &lpc32xx_mmu_config_table [i]); |
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164 | } |
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165 | |
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166 | /* Enable MMU and cache */ |
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167 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
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168 | arm_cp15_set_control(ctrl); |
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169 | } |
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170 | #endif |
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171 | |
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172 | static void BSP_START_SECTION setup_mmu_and_cache(void) |
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173 | { |
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174 | uint32_t ctrl = 0; |
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175 | |
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176 | /* Disable MMU and cache, basic settings */ |
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177 | ctrl = arm_cp15_get_control(); |
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178 | ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C |
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179 | | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M); |
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180 | ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A; |
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181 | arm_cp15_set_control(ctrl); |
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182 | |
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183 | arm_cp15_cache_invalidate(); |
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184 | arm_cp15_tlb_invalidate(); |
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185 | |
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186 | #ifndef LPC32XX_DISABLE_MMU |
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187 | setup_translation_table_and_enable_mmu(ctrl); |
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188 | #endif |
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189 | } |
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190 | |
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191 | #if LPC32XX_OSCILLATOR_MAIN != 13000000U |
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192 | #error "unexpected main oscillator frequency" |
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193 | #endif |
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194 | |
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195 | static void BSP_START_SECTION setup_pll(void) |
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196 | { |
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197 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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198 | |
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199 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0) { |
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200 | /* Enable HCLK PLL */ |
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201 | LPC32XX_HCLKPLL_CTRL = HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1); |
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202 | while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) { |
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203 | /* Wait */ |
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204 | } |
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205 | |
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206 | /* Setup HCLK divider */ |
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207 | LPC32XX_HCLKDIV_CTRL = HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1); |
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208 | |
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209 | /* Enable HCLK PLL output */ |
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210 | LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE; |
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211 | } |
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212 | } |
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213 | |
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214 | void BSP_START_SECTION bsp_start_hook_0(void) |
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215 | { |
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216 | setup_pll(); |
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217 | setup_mmu_and_cache(); |
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218 | } |
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219 | |
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220 | static void BSP_START_SECTION setup_uarts(void) |
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221 | { |
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222 | uint32_t uartclk_ctrl = 0; |
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223 | |
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224 | #ifdef LPC32XX_CONFIG_U3CLK |
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225 | uartclk_ctrl |= 1U << 0; |
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226 | LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK; |
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227 | #endif |
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228 | #ifdef LPC32XX_CONFIG_U4CLK |
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229 | uartclk_ctrl |= 1U << 1; |
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230 | LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK; |
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231 | #endif |
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232 | #ifdef LPC32XX_CONFIG_U5CLK |
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233 | uartclk_ctrl |= 1U << 2; |
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234 | LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; |
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235 | #endif |
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236 | #ifdef LPC32XX_CONFIG_U6CLK |
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237 | uartclk_ctrl |= 1U << 3; |
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238 | LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK; |
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239 | #endif |
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240 | |
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241 | #ifdef LPC32XX_CONFIG_UART_CLKMODE |
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242 | LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE; |
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243 | #endif |
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244 | |
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245 | LPC32XX_UARTCLK_CTRL = uartclk_ctrl; |
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246 | LPC32XX_UART_CTRL = 0x0; |
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247 | LPC32XX_UART_LOOP = 0x0; |
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248 | |
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249 | #ifdef LPC32XX_CONFIG_U5CLK |
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250 | /* Clock is already set in LPC32XX_U5CLK */ |
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251 | BSP_CONSOLE_UART_INIT(0x01); |
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252 | #endif |
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253 | } |
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254 | |
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255 | static void BSP_START_SECTION setup_timer(void) |
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256 | { |
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257 | volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; |
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258 | |
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259 | LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3); |
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260 | |
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261 | timer->tcr = LPC_TIMER_TCR_RST; |
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262 | timer->ctcr = 0x0; |
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263 | timer->pr = 0x0; |
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264 | timer->ir = 0xff; |
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265 | timer->mcr = 0x0; |
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266 | timer->ccr = 0x0; |
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267 | timer->tcr = LPC_TIMER_TCR_EN; |
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268 | } |
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269 | |
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270 | void BSP_START_SECTION bsp_start_hook_1(void) |
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271 | { |
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272 | setup_uarts(); |
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273 | setup_timer(); |
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274 | |
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275 | /* Copy .text section */ |
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276 | arm_cp15_instruction_cache_invalidate(); |
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277 | bsp_start_memcpy( |
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278 | (int *) bsp_section_text_begin, |
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279 | (const int *) bsp_section_text_load_begin, |
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280 | (size_t) bsp_section_text_size |
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281 | ); |
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282 | |
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283 | /* Copy .rodata section */ |
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284 | arm_cp15_instruction_cache_invalidate(); |
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285 | bsp_start_memcpy( |
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286 | (int *) bsp_section_rodata_begin, |
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287 | (const int *) bsp_section_rodata_load_begin, |
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288 | (size_t) bsp_section_rodata_size |
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289 | ); |
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290 | |
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291 | /* Copy .data section */ |
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292 | arm_cp15_instruction_cache_invalidate(); |
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293 | bsp_start_memcpy( |
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294 | (int *) bsp_section_data_begin, |
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295 | (const int *) bsp_section_data_load_begin, |
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296 | (size_t) bsp_section_data_size |
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297 | ); |
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298 | |
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299 | /* Copy .fast section */ |
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300 | arm_cp15_instruction_cache_invalidate(); |
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301 | bsp_start_memcpy( |
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302 | (int *) bsp_section_fast_begin, |
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303 | (const int *) bsp_section_fast_load_begin, |
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304 | (size_t) bsp_section_fast_size |
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305 | ); |
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306 | |
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307 | /* Clear .bss section */ |
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308 | clear_bss(); |
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309 | |
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310 | /* At this point we can use objects outside the .start section */ |
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311 | } |
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