1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_lpc32xx |
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5 | * |
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6 | * @brief System clocks. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/lpc32xx.h> |
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25 | |
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26 | uint32_t lpc32xx_sysclk(void) |
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27 | { |
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28 | uint32_t sysclk_ctrl = LPC32XX_SYSCLK_CTRL; |
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29 | |
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30 | return (sysclk_ctrl & 0x1) == 0 ? |
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31 | LPC32XX_OSCILLATOR_MAIN |
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32 | : (397 * LPC32XX_OSCILLATOR_RTC); |
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33 | } |
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34 | |
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35 | uint32_t lpc32xx_hclkpll_clk(void) |
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36 | { |
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37 | uint32_t sysclk = lpc32xx_sysclk(); |
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38 | uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL; |
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39 | uint32_t m = HCLK_PLL_M_GET(hclkpll_ctrl) + 1; |
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40 | uint32_t n = HCLK_PLL_N_GET(hclkpll_ctrl) + 1; |
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41 | uint32_t p = 1U << HCLK_PLL_P_GET(hclkpll_ctrl); |
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42 | uint32_t hclkpll_clk = 0; |
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43 | |
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44 | if ((hclkpll_ctrl & HCLK_PLL_BYPASS) != 0) { |
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45 | if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) { |
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46 | hclkpll_clk = sysclk; |
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47 | } else { |
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48 | hclkpll_clk = sysclk / (2 * p); |
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49 | } |
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50 | } else { |
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51 | if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) { |
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52 | hclkpll_clk = (m * sysclk) / n; |
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53 | } else { |
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54 | if ((hclkpll_ctrl & HCLK_PLL_FBD_FCLKOUT) != 0) { |
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55 | hclkpll_clk = m * (sysclk / n); |
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56 | } else { |
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57 | hclkpll_clk = (m / (2 * p)) * (sysclk / n); |
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58 | } |
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59 | } |
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60 | } |
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61 | |
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62 | return hclkpll_clk; |
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63 | } |
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64 | |
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65 | uint32_t lpc32xx_periph_clk(void) |
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66 | { |
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67 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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68 | uint32_t periph_clk = 0; |
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69 | |
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70 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) { |
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71 | uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL; |
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72 | uint32_t div = HCLK_DIV_PERIPH_CLK_GET(hclkdiv_ctrl) + 1; |
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73 | |
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74 | periph_clk = lpc32xx_hclkpll_clk() / div; |
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75 | } else { |
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76 | periph_clk = lpc32xx_sysclk(); |
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77 | } |
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78 | |
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79 | return periph_clk; |
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80 | } |
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81 | |
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82 | uint32_t lpc32xx_hclk(void) |
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83 | { |
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84 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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85 | uint32_t hclk = 0; |
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86 | |
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87 | if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) { |
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88 | hclk = lpc32xx_periph_clk(); |
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89 | } else { |
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90 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) { |
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91 | uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL; |
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92 | uint32_t div = 1U << HCLK_DIV_HCLK_GET(hclkdiv_ctrl); |
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93 | |
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94 | hclk = lpc32xx_hclkpll_clk() / div; |
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95 | } else { |
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96 | hclk = lpc32xx_sysclk(); |
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97 | } |
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98 | } |
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99 | |
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100 | return hclk; |
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101 | } |
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102 | |
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103 | uint32_t lpc32xx_arm_clk(void) |
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104 | { |
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105 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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106 | uint32_t arm_clk = 0; |
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107 | |
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108 | if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) { |
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109 | arm_clk = lpc32xx_periph_clk(); |
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110 | } else { |
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111 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) { |
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112 | arm_clk = lpc32xx_hclkpll_clk(); |
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113 | } else { |
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114 | arm_clk = lpc32xx_sysclk(); |
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115 | } |
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116 | } |
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117 | |
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118 | return arm_clk; |
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119 | } |
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120 | |
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121 | uint32_t lpc32xx_ddram_clk(void) |
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122 | { |
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123 | uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL; |
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124 | uint32_t div = HCLK_DIV_DDRAM_CLK_GET(hclkdiv_ctrl); |
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125 | uint32_t ddram_clk = 0; |
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126 | |
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127 | if (div != 0) { |
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128 | uint32_t pwr_ctrl = LPC32XX_PWR_CTRL; |
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129 | |
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130 | if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) { |
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131 | ddram_clk = lpc32xx_hclkpll_clk(); |
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132 | } else { |
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133 | ddram_clk = lpc32xx_sysclk(); |
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134 | } |
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135 | |
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136 | ddram_clk /= div; |
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137 | } |
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138 | |
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139 | return ddram_clk; |
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140 | } |
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