source: rtems/c/src/lib/libbsp/arm/lpc32xx/misc/system-clocks.c @ c499856

4.11
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm_lpc32xx
5 *
6 * @brief System clocks.
7 */
8
9/*
10 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <bsp.h>
24#include <bsp/lpc32xx.h>
25
26uint32_t lpc32xx_sysclk(void)
27{
28  uint32_t sysclk_ctrl = LPC32XX_SYSCLK_CTRL;
29
30  return (sysclk_ctrl & 0x1) == 0 ?
31    LPC32XX_OSCILLATOR_MAIN
32      : (397 * LPC32XX_OSCILLATOR_RTC);
33}
34
35uint32_t lpc32xx_hclkpll_clk(void)
36{
37  uint32_t sysclk = lpc32xx_sysclk();
38  uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL;
39  uint32_t m = HCLK_PLL_M_GET(hclkpll_ctrl) + 1;
40  uint32_t n = HCLK_PLL_N_GET(hclkpll_ctrl) + 1;
41  uint32_t p = 1U << HCLK_PLL_P_GET(hclkpll_ctrl);
42  uint32_t hclkpll_clk = 0;
43
44  if ((hclkpll_ctrl & HCLK_PLL_BYPASS) != 0) {
45    if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) {
46      hclkpll_clk = sysclk;
47    } else {
48      hclkpll_clk = sysclk / (2 * p);
49    }
50  } else {
51    if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) {
52      hclkpll_clk = (m * sysclk) / n;
53    } else {
54      if ((hclkpll_ctrl & HCLK_PLL_FBD_FCLKOUT) != 0) {
55        hclkpll_clk = m * (sysclk / n);
56      } else {
57        hclkpll_clk = (m / (2 * p)) * (sysclk / n);
58      }
59    }
60  }
61
62  return hclkpll_clk;
63}
64
65uint32_t lpc32xx_periph_clk(void)
66{
67  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
68  uint32_t periph_clk = 0;
69
70  if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
71    uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
72    uint32_t div = HCLK_DIV_PERIPH_CLK_GET(hclkdiv_ctrl) + 1;
73
74    periph_clk = lpc32xx_hclkpll_clk() / div;
75  } else {
76    periph_clk = lpc32xx_sysclk();
77  }
78
79  return periph_clk;
80}
81
82uint32_t lpc32xx_hclk(void)
83{
84  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
85  uint32_t hclk = 0;
86
87  if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) {
88    hclk = lpc32xx_periph_clk();
89  } else {
90    if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
91      uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
92      uint32_t div = 1U << HCLK_DIV_HCLK_GET(hclkdiv_ctrl);
93
94      hclk = lpc32xx_hclkpll_clk() / div;
95    } else {
96      hclk = lpc32xx_sysclk();
97    }
98  }
99
100  return hclk;
101}
102
103uint32_t lpc32xx_arm_clk(void)
104{
105  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
106  uint32_t arm_clk = 0;
107
108  if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) {
109    arm_clk = lpc32xx_periph_clk();
110  } else {
111    if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
112      arm_clk = lpc32xx_hclkpll_clk();
113    } else {
114      arm_clk = lpc32xx_sysclk();
115    }
116  }
117
118  return arm_clk;
119}
120
121uint32_t lpc32xx_ddram_clk(void)
122{
123  uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
124  uint32_t div = HCLK_DIV_DDRAM_CLK_GET(hclkdiv_ctrl);
125  uint32_t ddram_clk = 0;
126
127  if (div != 0) {
128    uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
129
130    if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
131      ddram_clk = lpc32xx_hclkpll_clk();
132    } else {
133      ddram_clk = lpc32xx_sysclk();
134    }
135
136    ddram_clk /= div;
137  }
138
139  return ddram_clk;
140}
Note: See TracBrowser for help on using the repository browser.