1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_i2c |
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5 | * |
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6 | * @brief I2C support implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <rtems.h> |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <bsp/i2c.h> |
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27 | |
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28 | void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c) |
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29 | { |
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30 | i2c->ctrl = I2C_CTRL_RESET; |
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31 | } |
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32 | |
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33 | rtems_status_code lpc32xx_i2c_init( |
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34 | volatile lpc32xx_i2c *i2c, |
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35 | unsigned clock_in_hz |
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36 | ) |
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37 | { |
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38 | uint32_t i2cclk = 0; |
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39 | |
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40 | if (i2c == &lpc32xx.i2c_1) { |
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41 | i2cclk |= I2CCLK_1_EN | I2CCLK_1_HIGH_DRIVE; |
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42 | } else if (i2c == &lpc32xx.i2c_2) { |
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43 | i2cclk |= I2CCLK_2_EN | I2CCLK_2_HIGH_DRIVE; |
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44 | } else { |
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45 | return RTEMS_INVALID_ID; |
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46 | } |
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47 | |
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48 | LPC32XX_I2CCLK_CTRL |= i2cclk; |
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49 | |
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50 | lpc32xx_i2c_reset(i2c); |
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51 | |
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52 | return lpc32xx_i2c_clock(i2c, clock_in_hz); |
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53 | } |
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54 | |
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55 | rtems_status_code lpc32xx_i2c_clock( |
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56 | volatile lpc32xx_i2c *i2c, |
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57 | unsigned clock_in_hz |
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58 | ) |
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59 | { |
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60 | uint32_t clk_div = lpc32xx_hclk() / clock_in_hz; |
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61 | uint32_t clk_lo = 0; |
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62 | uint32_t clk_hi = 0; |
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63 | |
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64 | switch (clock_in_hz) { |
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65 | case 100000: |
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66 | clk_lo = clk_div / 2; |
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67 | break; |
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68 | case 400000: |
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69 | clk_lo = (64 * clk_div) / 100; |
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70 | break; |
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71 | default: |
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72 | return RTEMS_INVALID_CLOCK; |
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73 | } |
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74 | |
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75 | clk_hi = clk_div - clk_lo; |
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76 | |
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77 | i2c->clk_lo = clk_lo; |
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78 | i2c->clk_hi = clk_hi; |
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79 | |
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80 | return RTEMS_SUCCESSFUL; |
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81 | } |
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82 | |
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83 | static rtems_status_code wait_for_transaction_done(volatile lpc32xx_i2c *i2c) |
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84 | { |
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85 | uint32_t stat = 0; |
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86 | |
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87 | do { |
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88 | stat = i2c->stat; |
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89 | } while ((stat & I2C_STAT_TDI) == 0); |
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90 | |
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91 | if ((stat & I2C_STAT_TFE) != 0) { |
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92 | i2c->stat = I2C_STAT_TDI; |
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93 | |
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94 | return RTEMS_SUCCESSFUL; |
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95 | } else { |
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96 | lpc32xx_i2c_reset(i2c); |
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97 | |
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98 | return RTEMS_IO_ERROR; |
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99 | } |
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100 | } |
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101 | |
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102 | static rtems_status_code tx(volatile lpc32xx_i2c *i2c, uint32_t data) |
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103 | { |
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104 | uint32_t stat = 0; |
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105 | |
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106 | do { |
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107 | stat = i2c->stat; |
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108 | } while ((stat & (I2C_STAT_TFE | I2C_STAT_TDI)) == 0); |
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109 | |
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110 | if ((stat & I2C_STAT_TDI) == 0) { |
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111 | i2c->rx_or_tx = data; |
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112 | |
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113 | return RTEMS_SUCCESSFUL; |
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114 | } else { |
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115 | lpc32xx_i2c_reset(i2c); |
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116 | |
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117 | return RTEMS_IO_ERROR; |
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118 | } |
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119 | } |
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120 | |
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121 | rtems_status_code lpc32xx_i2c_write_start( |
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122 | volatile lpc32xx_i2c *i2c, |
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123 | unsigned addr |
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124 | ) |
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125 | { |
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126 | return tx(i2c, I2C_TX_ADDR(addr) | I2C_TX_START); |
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127 | } |
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128 | |
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129 | rtems_status_code lpc32xx_i2c_read_start( |
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130 | volatile lpc32xx_i2c *i2c, |
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131 | unsigned addr |
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132 | ) |
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133 | { |
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134 | return tx(i2c, I2C_TX_ADDR(addr) | I2C_TX_START | I2C_TX_READ); |
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135 | } |
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136 | |
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137 | rtems_status_code lpc32xx_i2c_write_with_optional_stop( |
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138 | volatile lpc32xx_i2c *i2c, |
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139 | const uint8_t *out, |
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140 | size_t n, |
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141 | bool stop |
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142 | ) |
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143 | { |
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144 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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145 | size_t i = 0; |
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146 | |
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147 | for (i = 0; i < n - 1 && sc == RTEMS_SUCCESSFUL; ++i) { |
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148 | sc = tx(i2c, out [i]); |
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149 | } |
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150 | |
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151 | if (sc == RTEMS_SUCCESSFUL) { |
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152 | uint32_t stop_flag = stop ? I2C_TX_STOP : 0; |
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153 | |
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154 | sc = tx(i2c, out [n - 1] | stop_flag); |
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155 | } |
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156 | |
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157 | if (stop && sc == RTEMS_SUCCESSFUL) { |
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158 | sc = wait_for_transaction_done(i2c); |
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159 | } |
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160 | |
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161 | return sc; |
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162 | } |
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163 | |
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164 | static bool can_tx_for_rx(volatile lpc32xx_i2c *i2c) |
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165 | { |
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166 | return (i2c->stat & (I2C_STAT_TFF | I2C_STAT_RFF)) == 0; |
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167 | } |
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168 | |
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169 | static bool can_rx(volatile lpc32xx_i2c *i2c) |
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170 | { |
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171 | return (i2c->stat & I2C_STAT_RFE) == 0; |
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172 | } |
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173 | |
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174 | rtems_status_code lpc32xx_i2c_read_with_optional_stop( |
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175 | volatile lpc32xx_i2c *i2c, |
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176 | uint8_t *in, |
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177 | size_t n, |
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178 | bool stop |
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179 | ) |
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180 | { |
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181 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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182 | size_t last = n - 1; |
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183 | size_t rx = 0; |
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184 | size_t tx = 0; |
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185 | |
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186 | if (!stop) { |
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187 | return RTEMS_NOT_IMPLEMENTED; |
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188 | } |
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189 | |
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190 | while (rx <= last) { |
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191 | while (tx < last && can_tx_for_rx(i2c)) { |
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192 | i2c->rx_or_tx = 0; |
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193 | ++tx; |
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194 | } |
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195 | |
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196 | if (tx == last && can_tx_for_rx(i2c)) { |
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197 | uint32_t stop_flag = stop ? I2C_TX_STOP : 0; |
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198 | |
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199 | i2c->rx_or_tx = stop_flag; |
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200 | ++tx; |
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201 | } |
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202 | |
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203 | while (rx <= last && can_rx(i2c)) { |
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204 | in [rx] = (uint8_t) i2c->rx_or_tx; |
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205 | ++rx; |
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206 | } |
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207 | } |
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208 | |
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209 | if (stop) { |
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210 | sc = wait_for_transaction_done(i2c); |
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211 | } |
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212 | |
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213 | return sc; |
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214 | } |
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215 | |
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216 | rtems_status_code lpc32xx_i2c_write_and_read( |
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217 | volatile lpc32xx_i2c *i2c, |
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218 | unsigned addr, |
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219 | const uint8_t *out, |
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220 | size_t out_size, |
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221 | uint8_t *in, |
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222 | size_t in_size |
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223 | ) |
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224 | { |
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225 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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226 | |
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227 | if (out_size > 0) { |
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228 | bool stop = in_size == 0; |
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229 | |
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230 | sc = lpc32xx_i2c_write_start(i2c, addr); |
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231 | if (sc != RTEMS_SUCCESSFUL) { |
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232 | return sc; |
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233 | } |
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234 | |
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235 | sc = lpc32xx_i2c_write_with_optional_stop(i2c, out, out_size, stop); |
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236 | if (sc != RTEMS_SUCCESSFUL) { |
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237 | return sc; |
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238 | } |
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239 | } |
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240 | |
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241 | if (in_size > 0) { |
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242 | sc = lpc32xx_i2c_read_start(i2c, addr); |
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243 | if (sc != RTEMS_SUCCESSFUL) { |
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244 | return sc; |
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245 | } |
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246 | |
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247 | lpc32xx_i2c_read_with_optional_stop(i2c, in, in_size, true); |
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248 | } |
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249 | |
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250 | return RTEMS_SUCCESSFUL; |
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251 | } |
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