[3103d4cb] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc32xx_emc |
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| 5 | * |
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| 6 | * @brief EMC support implementation. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2010 |
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| 11 | * embedded brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * <rtems@embedded-brains.de> |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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[c499856] | 19 | * http://www.rtems.org/license/LICENSE. |
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[3103d4cb] | 20 | */ |
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| 21 | |
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| 22 | #include <bsp/emc.h> |
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| 23 | |
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| 24 | #include <bsp.h> |
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| 25 | #include <bsp/mmu.h> |
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| 26 | |
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[76134c5] | 27 | static volatile lpc_emc *const emc = &lpc32xx.emc; |
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| 28 | |
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| 29 | static volatile lpc32xx_emc_ahb *const emc_ahb = &lpc32xx.emc_ahb [0]; |
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[3103d4cb] | 30 | |
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| 31 | static void dynamic_init(const lpc32xx_emc_dynamic_config *cfg) |
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| 32 | { |
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| 33 | uint32_t chip_begin = LPC32XX_BASE_EMC_DYCS_0; |
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| 34 | uint32_t dynamiccontrol = (cfg->control | EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS) |
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| 35 | & ~EMC_DYN_CTRL_I_MASK; |
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| 36 | size_t i = 0; |
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| 37 | |
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| 38 | LPC32XX_SDRAMCLK_CTRL = cfg->sdramclk_ctrl; |
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| 39 | |
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| 40 | emc->dynamicreadconfig = cfg->readconfig; |
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| 41 | |
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| 42 | /* Timings */ |
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| 43 | emc->dynamictrp = cfg->trp; |
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| 44 | emc->dynamictras = cfg->tras; |
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| 45 | emc->dynamictsrex = cfg->tsrex; |
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| 46 | emc->dynamictwr = cfg->twr; |
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| 47 | emc->dynamictrc = cfg->trc; |
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| 48 | emc->dynamictrfc = cfg->trfc; |
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| 49 | emc->dynamictxsr = cfg->txsr; |
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| 50 | emc->dynamictrrd = cfg->trrd; |
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| 51 | emc->dynamictmrd = cfg->tmrd; |
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| 52 | emc->dynamictcdlr = cfg->tcdlr; |
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| 53 | for (i = 0; i < EMC_DYN_CHIP_COUNT; ++i) { |
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| 54 | if (cfg->chip [i].size != 0) { |
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| 55 | emc->dynamic [i].config = cfg->chip [i].config; |
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| 56 | emc->dynamic [i].rascas = cfg->chip [i].rascas; |
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| 57 | } |
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| 58 | } |
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| 59 | |
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| 60 | /* NOP period */ |
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| 61 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP; |
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| 62 | lpc32xx_micro_seconds_delay(cfg->nop_time_in_us); |
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| 63 | |
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| 64 | /* Precharge */ |
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| 65 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL; |
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| 66 | emc->dynamicrefresh = 1; |
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| 67 | /* FIXME: Why a delay, why this value? */ |
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| 68 | lpc32xx_micro_seconds_delay(10); |
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| 69 | |
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| 70 | /* Refresh timing */ |
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| 71 | emc->dynamicrefresh = cfg->refresh; |
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| 72 | /* FIXME: Why a delay, why this value? */ |
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| 73 | lpc32xx_micro_seconds_delay(16); |
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| 74 | |
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| 75 | /* Set modes */ |
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| 76 | for (i = 0; i < EMC_DYN_CHIP_COUNT; ++i) { |
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| 77 | if (cfg->chip [i].size != 0) { |
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[f140fdc] | 78 | lpc32xx_set_translation_table_entries( |
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| 79 | (void *) chip_begin, |
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| 80 | (void *) (chip_begin + cfg->chip [i].size), |
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| 81 | LPC32XX_MMU_READ_WRITE |
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| 82 | ); |
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[3103d4cb] | 83 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE; |
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[f140fdc] | 84 | *(volatile uint32_t *)(chip_begin + cfg->chip [i].mode); |
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[3103d4cb] | 85 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE; |
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[f140fdc] | 86 | *(volatile uint32_t *)(chip_begin + cfg->chip [i].extmode); |
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[3103d4cb] | 87 | } |
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| 88 | chip_begin += 0x20000000; |
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| 89 | } |
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| 90 | |
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| 91 | emc->dynamiccontrol = cfg->control; |
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| 92 | } |
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| 93 | |
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| 94 | void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg) |
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| 95 | { |
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| 96 | /* Enable buffers in AHB ports */ |
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[76134c5] | 97 | emc_ahb [0].control = EMC_AHB_PORT_BUFF_EN; |
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| 98 | emc_ahb [3].control = EMC_AHB_PORT_BUFF_EN; |
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| 99 | emc_ahb [4].control = EMC_AHB_PORT_BUFF_EN; |
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[3103d4cb] | 100 | |
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| 101 | /* Set AHB port timeouts */ |
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[76134c5] | 102 | emc_ahb [0].timeout = EMC_AHB_TIMEOUT(32); |
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| 103 | emc_ahb [3].timeout = EMC_AHB_TIMEOUT(32); |
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| 104 | emc_ahb [4].timeout = EMC_AHB_TIMEOUT(32); |
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[3103d4cb] | 105 | |
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| 106 | /* Enable EMC */ |
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[76134c5] | 107 | emc->control = EMC_CTRL_E, |
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[3103d4cb] | 108 | emc->config = 0; |
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| 109 | |
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| 110 | dynamic_init(dyn_cfg); |
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| 111 | } |
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