1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_interrupt |
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5 | * |
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6 | * @brief Interrupt support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #include <rtems/score/armv4.h> |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <bsp/irq.h> |
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26 | #include <bsp/irq-generic.h> |
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27 | #include <bsp/lpc32xx.h> |
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28 | #include <bsp/linker-symbols.h> |
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29 | #include <bsp/mmu.h> |
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30 | |
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31 | /* |
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32 | * Mask out SIC 1 and 2 IRQ request. There is no need to mask out the FIQ, |
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33 | * since a pending FIQ would be a fatal error. The default handler will be |
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34 | * invoked in this case. |
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35 | */ |
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36 | #define LPC32XX_MIC_STATUS_MASK (~0x3U) |
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37 | |
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38 | typedef union { |
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39 | struct { |
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40 | uint32_t mic; |
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41 | uint32_t sic_1; |
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42 | uint32_t sic_2; |
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43 | } field; |
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44 | uint32_t fields_table [LPC32XX_IRQ_MODULE_COUNT]; |
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45 | } lpc32xx_irq_fields; |
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46 | |
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47 | static uint8_t lpc32xx_irq_priority_table [LPC32XX_IRQ_COUNT]; |
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48 | |
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49 | static lpc32xx_irq_fields lpc32xx_irq_priority_masks [LPC32XX_IRQ_PRIORITY_COUNT]; |
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50 | |
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51 | static lpc32xx_irq_fields lpc32xx_irq_enable; |
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52 | |
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53 | static inline bool lpc32xx_irq_is_valid(rtems_vector_number vector) |
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54 | { |
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55 | return vector <= BSP_INTERRUPT_VECTOR_MAX; |
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56 | } |
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57 | |
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58 | static inline bool lpc32xx_irq_priority_is_valid(unsigned priority) |
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59 | { |
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60 | return priority <= LPC32XX_IRQ_PRIORITY_LOWEST; |
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61 | } |
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62 | |
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63 | #define LPC32XX_IRQ_BIT_OPS_DEFINE \ |
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64 | unsigned bit = index & 0x1fU; \ |
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65 | unsigned module = index >> 5 |
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66 | |
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67 | #define LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE \ |
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68 | LPC32XX_IRQ_BIT_OPS_DEFINE; \ |
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69 | unsigned module_offset = module << 14; \ |
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70 | volatile uint32_t *reg = (volatile uint32_t *) \ |
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71 | ((volatile char *) &lpc32xx.mic + module_offset + register_offset) |
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72 | |
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73 | #define LPC32XX_IRQ_OFFSET_ER 0U |
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74 | #define LPC32XX_IRQ_OFFSET_RSR 4U |
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75 | #define LPC32XX_IRQ_OFFSET_SR 8U |
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76 | #define LPC32XX_IRQ_OFFSET_APR 12U |
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77 | #define LPC32XX_IRQ_OFFSET_ATR 16U |
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78 | #define LPC32XX_IRQ_OFFSET_ITR 20U |
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79 | |
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80 | static inline bool lpc32xx_irq_is_bit_set_in_register(unsigned index, unsigned register_offset) |
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81 | { |
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82 | LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; |
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83 | |
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84 | return *reg & (1U << bit); |
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85 | } |
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86 | |
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87 | static inline void lpc32xx_irq_set_bit_in_register(unsigned index, unsigned register_offset) |
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88 | { |
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89 | LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; |
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90 | |
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91 | *reg |= 1U << bit; |
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92 | } |
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93 | |
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94 | static inline void lpc32xx_irq_clear_bit_in_register(unsigned index, unsigned register_offset) |
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95 | { |
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96 | LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; |
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97 | |
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98 | *reg &= ~(1U << bit); |
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99 | } |
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100 | |
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101 | static inline void lpc32xx_irq_set_bit_in_field(unsigned index, lpc32xx_irq_fields *fields) |
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102 | { |
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103 | LPC32XX_IRQ_BIT_OPS_DEFINE; |
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104 | |
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105 | fields->fields_table [module] |= 1U << bit; |
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106 | } |
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107 | |
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108 | static inline void lpc32xx_irq_clear_bit_in_field(unsigned index, lpc32xx_irq_fields *fields) |
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109 | { |
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110 | LPC32XX_IRQ_BIT_OPS_DEFINE; |
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111 | |
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112 | fields->fields_table [module] &= ~(1U << bit); |
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113 | } |
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114 | |
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115 | static inline unsigned lpc32xx_irq_get_index(uint32_t val) |
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116 | { |
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117 | ARM_SWITCH_REGISTERS; |
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118 | |
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119 | __asm__ volatile ( |
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120 | ARM_SWITCH_TO_ARM |
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121 | "clz %[val], %[val]\n" |
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122 | "rsb %[val], %[val], #31\n" |
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123 | ARM_SWITCH_BACK |
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124 | : [val] "=r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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125 | : "[val]" (val) |
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126 | ); |
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127 | |
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128 | return val; |
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129 | } |
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130 | |
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131 | void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority) |
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132 | { |
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133 | if (lpc32xx_irq_is_valid(vector)) { |
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134 | rtems_interrupt_level level; |
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135 | unsigned i = 0; |
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136 | |
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137 | if (priority > LPC32XX_IRQ_PRIORITY_LOWEST) { |
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138 | priority = LPC32XX_IRQ_PRIORITY_LOWEST; |
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139 | } |
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140 | |
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141 | lpc32xx_irq_priority_table [vector] = (uint8_t) priority; |
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142 | |
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143 | for (i = LPC32XX_IRQ_PRIORITY_HIGHEST; i <= priority; ++i) { |
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144 | rtems_interrupt_disable(level); |
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145 | lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]); |
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146 | rtems_interrupt_enable(level); |
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147 | } |
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148 | |
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149 | for (i = priority + 1; i <= LPC32XX_IRQ_PRIORITY_LOWEST; ++i) { |
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150 | rtems_interrupt_disable(level); |
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151 | lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]); |
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152 | rtems_interrupt_enable(level); |
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153 | } |
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154 | } |
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155 | } |
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156 | |
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157 | unsigned lpc32xx_irq_get_priority(rtems_vector_number vector) |
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158 | { |
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159 | if (lpc32xx_irq_is_valid(vector)) { |
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160 | return lpc32xx_irq_priority_table [vector]; |
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161 | } else { |
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162 | return LPC32XX_IRQ_PRIORITY_LOWEST; |
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163 | } |
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164 | } |
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165 | |
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166 | void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity) |
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167 | { |
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168 | if (lpc32xx_irq_is_valid(vector)) { |
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169 | rtems_interrupt_level level; |
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170 | |
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171 | rtems_interrupt_disable(level); |
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172 | if (activation_polarity == LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE) { |
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173 | lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR); |
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174 | } else { |
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175 | lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR); |
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176 | } |
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177 | rtems_interrupt_enable(level); |
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178 | } |
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179 | } |
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180 | |
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181 | lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector) |
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182 | { |
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183 | if (lpc32xx_irq_is_valid(vector)) { |
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184 | if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_APR)) { |
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185 | return LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE; |
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186 | } else { |
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187 | return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE; |
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188 | } |
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189 | } else { |
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190 | return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE; |
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191 | } |
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192 | } |
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193 | |
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194 | void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type) |
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195 | { |
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196 | if (lpc32xx_irq_is_valid(vector)) { |
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197 | rtems_interrupt_level level; |
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198 | |
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199 | rtems_interrupt_disable(level); |
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200 | if (activation_type == LPC32XX_IRQ_EDGE_SENSITIVE) { |
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201 | lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR); |
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202 | } else { |
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203 | lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR); |
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204 | } |
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205 | rtems_interrupt_enable(level); |
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206 | } |
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207 | } |
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208 | |
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209 | lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector) |
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210 | { |
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211 | if (lpc32xx_irq_is_valid(vector)) { |
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212 | if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_ATR)) { |
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213 | return LPC32XX_IRQ_EDGE_SENSITIVE; |
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214 | } else { |
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215 | return LPC32XX_IRQ_LEVEL_SENSITIVE; |
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216 | } |
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217 | } else { |
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218 | return LPC32XX_IRQ_LEVEL_SENSITIVE; |
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219 | } |
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220 | } |
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221 | |
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222 | void bsp_interrupt_dispatch(void) |
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223 | { |
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224 | uint32_t status = lpc32xx.mic.sr & LPC32XX_MIC_STATUS_MASK; |
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225 | uint32_t er_mic = lpc32xx.mic.er; |
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226 | uint32_t er_sic_1 = lpc32xx.sic_1.er; |
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227 | uint32_t er_sic_2 = lpc32xx.sic_2.er; |
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228 | uint32_t psr = 0; |
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229 | lpc32xx_irq_fields *masks = NULL; |
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230 | rtems_vector_number vector = 0; |
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231 | unsigned priority = 0; |
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232 | |
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233 | if (status != 0) { |
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234 | vector = lpc32xx_irq_get_index(status); |
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235 | } else { |
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236 | status = lpc32xx.sic_1.sr; |
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237 | if (status != 0) { |
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238 | vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_1; |
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239 | } else { |
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240 | status = lpc32xx.sic_2.sr; |
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241 | if (status != 0) { |
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242 | vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_2; |
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243 | } else { |
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244 | return; |
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245 | } |
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246 | } |
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247 | } |
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248 | |
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249 | priority = lpc32xx_irq_priority_table [vector]; |
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250 | |
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251 | masks = &lpc32xx_irq_priority_masks [priority]; |
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252 | |
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253 | lpc32xx.mic.er = er_mic & masks->field.mic; |
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254 | lpc32xx.sic_1.er = er_sic_1 & masks->field.sic_1; |
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255 | lpc32xx.sic_2.er = er_sic_2 & masks->field.sic_2; |
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256 | |
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257 | psr = _ARMV4_Status_irq_enable(); |
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258 | |
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259 | bsp_interrupt_handler_dispatch(vector); |
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260 | |
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261 | _ARMV4_Status_restore(psr); |
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262 | |
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263 | lpc32xx.mic.er = er_mic & lpc32xx_irq_enable.field.mic; |
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264 | lpc32xx.sic_1.er = er_sic_1 & lpc32xx_irq_enable.field.sic_1; |
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265 | lpc32xx.sic_2.er = er_sic_2 & lpc32xx_irq_enable.field.sic_2; |
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266 | } |
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267 | |
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268 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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269 | { |
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270 | if (lpc32xx_irq_is_valid(vector)) { |
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271 | rtems_interrupt_level level; |
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272 | |
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273 | rtems_interrupt_disable(level); |
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274 | lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER); |
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275 | lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_enable); |
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276 | rtems_interrupt_enable(level); |
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277 | } |
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278 | |
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279 | return RTEMS_SUCCESSFUL; |
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280 | } |
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281 | |
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282 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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283 | { |
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284 | if (lpc32xx_irq_is_valid(vector)) { |
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285 | rtems_interrupt_level level; |
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286 | |
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287 | rtems_interrupt_disable(level); |
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288 | lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_enable); |
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289 | lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER); |
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290 | rtems_interrupt_enable(level); |
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291 | } |
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292 | |
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293 | return RTEMS_SUCCESSFUL; |
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294 | } |
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295 | |
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296 | void lpc32xx_set_exception_handler( |
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297 | Arm_symbolic_exception_name exception, |
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298 | void (*handler)(void) |
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299 | ) |
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300 | { |
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301 | if ((unsigned) exception < MAX_EXCEPTIONS) { |
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302 | uint32_t *table = (uint32_t *) bsp_vector_table_begin + MAX_EXCEPTIONS; |
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303 | |
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304 | table [exception] = (uint32_t) handler; |
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305 | |
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306 | #ifndef LPC32XX_DISABLE_MMU |
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307 | rtems_cache_flush_multiple_data_lines(table, 64); |
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308 | rtems_cache_invalidate_multiple_instruction_lines(NULL, 64); |
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309 | #endif |
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310 | } |
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311 | } |
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312 | |
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313 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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314 | { |
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315 | size_t i = 0; |
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316 | |
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317 | /* Set default priority */ |
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318 | for (i = 0; i < LPC32XX_IRQ_COUNT; ++i) { |
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319 | lpc32xx_irq_priority_table [i] = LPC32XX_IRQ_PRIORITY_LOWEST; |
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320 | } |
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321 | |
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322 | /* Enable SIC 1 and 2 at all priorities */ |
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323 | for (i = 0; i < LPC32XX_IRQ_PRIORITY_COUNT; ++i) { |
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324 | lpc32xx_irq_priority_masks [i].field.mic = 0xc0000003; |
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325 | } |
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326 | |
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327 | /* Disable all interrupts except SIC 1 and 2 */ |
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328 | lpc32xx_irq_enable.field.sic_2 = 0x0; |
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329 | lpc32xx_irq_enable.field.sic_1 = 0x0; |
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330 | lpc32xx_irq_enable.field.mic = 0xc0000003; |
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331 | lpc32xx.sic_1.er = 0x0; |
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332 | lpc32xx.sic_2.er = 0x0; |
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333 | lpc32xx.mic.er = 0xc0000003; |
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334 | |
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335 | /* Set interrupt types to IRQ */ |
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336 | lpc32xx.mic.itr = 0x0; |
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337 | lpc32xx.sic_1.itr = 0x0; |
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338 | lpc32xx.sic_2.itr = 0x0; |
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339 | |
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340 | /* Set interrupt activation polarities */ |
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341 | lpc32xx.mic.apr = 0x3ff0efe0; |
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342 | lpc32xx.sic_1.apr = 0xfbd27184; |
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343 | lpc32xx.sic_2.apr = 0x801810c0; |
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344 | |
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345 | /* Set interrupt activation types */ |
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346 | lpc32xx.mic.atr = 0x0; |
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347 | lpc32xx.sic_1.atr = 0x26000; |
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348 | lpc32xx.sic_2.atr = 0x0; |
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349 | |
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350 | lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt); |
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351 | |
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352 | return RTEMS_SUCCESSFUL; |
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353 | } |
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