1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_nand_mlc |
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5 | * |
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6 | * @brief NAND MLC controller API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * Copyright (c) 2011 Stephan Hoffmann <sho@reLinux.de> |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.com/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #ifndef LIBBSP_ARM_LPC32XX_NAND_MLC_H |
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26 | #define LIBBSP_ARM_LPC32XX_NAND_MLC_H |
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27 | |
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28 | #include <rtems.h> |
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29 | |
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30 | #include <bsp/utility.h> |
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31 | |
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32 | #ifdef __cplusplus |
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33 | extern "C" { |
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34 | #endif /* __cplusplus */ |
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35 | |
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36 | /** |
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37 | * @defgroup lpc32xx_nand_mlc NAND MLC Controller |
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38 | * |
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39 | * @ingroup lpc32xx |
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40 | * |
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41 | * @brief NAND MLC Controller. |
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42 | * |
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43 | * Timing constraints: |
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44 | * |
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45 | * -# (WR_LOW + 1) / HCLK >= tWP |
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46 | * -# (WR_HIGH - WR_LOW) / HCLK >= tWH |
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47 | * -# (WR_LOW + 1) / HCLK + (WR_HIGH - WR_LOW) / HCLK >= tWC |
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48 | * -# (RD_LOW + 1) / HCLK >= tRP |
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49 | * -# (RD_LOW + 1) / HCLK >= tREA + tSU |
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50 | * -# (RD_HIGH - RD_LOW) / HCLK >= tREH |
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51 | * -# (RD_LOW + 1) / HCLK + (RD_HIGH - RD_LOW) / HCLK >= tRC |
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52 | * -# (RD_HIGH - RD_LOW) / HCLK + NAND_TA / HCLK >= tRHZ |
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53 | * -# BUSY_DELAY / HCLK >= max(tWB, tRB) |
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54 | * -# TCEA_DELAY / HCLK >= tCEA - tREA |
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55 | * |
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56 | * Known flash layouts (Format: SP = small pages, LP = large pages / address |
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57 | * cycles / pages per block): |
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58 | * |
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59 | * -# SP/3/32 |
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60 | * -# SP/4/32 |
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61 | * -# LP/4/64 |
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62 | * -# LP/5/64 |
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63 | * -# LP/5/128 |
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64 | * |
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65 | * @{ |
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66 | */ |
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67 | |
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68 | /** |
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69 | * @name MLC NAND Flash Dimensions |
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70 | * |
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71 | * @{ |
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72 | */ |
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73 | |
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74 | #define MLC_SMALL_PAGE_SIZE 528 |
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75 | #define MLC_SMALL_DATA_SIZE 512 |
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76 | #define MLC_SMALL_SPARE_SIZE 16 |
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77 | #define MLC_SMALL_DATA_WORD_COUNT (MLC_SMALL_DATA_SIZE / 4) |
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78 | #define MLC_SMALL_SPARE_WORD_COUNT (MLC_SMALL_SPARE_SIZE / 4) |
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79 | #define MLC_SMALL_PAGES_PER_LARGE_PAGE 4 |
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80 | #define MLC_LARGE_PAGE_SIZE \ |
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81 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_PAGE_SIZE) |
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82 | #define MLC_LARGE_DATA_SIZE \ |
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83 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_DATA_SIZE) |
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84 | #define MLC_LARGE_SPARE_SIZE \ |
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85 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_SPARE_SIZE) |
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86 | #define MLC_LARGE_DATA_WORD_COUNT (MLC_LARGE_DATA_SIZE / 4) |
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87 | #define MLC_LARGE_SPARE_WORD_COUNT (MLC_LARGE_SPARE_SIZE / 4) |
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88 | |
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89 | /** @} */ |
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90 | |
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91 | /** |
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92 | * @name NAND Flash Clock Control Register (FLASHCLK_CTRL) |
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93 | * |
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94 | * @{ |
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95 | */ |
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96 | |
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97 | #define FLASHCLK_IRQ_MLC BSP_BIT32(5) |
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98 | #define FLASHCLK_MLC_DMA_RNB BSP_BIT32(4) |
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99 | #define FLASHCLK_MLC_DMA_INT BSP_BIT32(3) |
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100 | #define FLASHCLK_SELECT_SLC BSP_BIT32(2) |
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101 | #define FLASHCLK_MLC_CLK_ENABLE BSP_BIT32(1) |
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102 | #define FLASHCLK_SLC_CLK_ENABLE BSP_BIT32(0) |
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103 | |
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104 | /** @} */ |
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105 | |
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106 | /** |
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107 | * @name MLC NAND Timing Register (MLC_TIME_REG) |
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108 | * |
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109 | * @{ |
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110 | */ |
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111 | |
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112 | #define MLC_TIME_WR_LOW(val) BSP_FLD32(val, 0, 3) |
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113 | #define MLC_TIME_WR_HIGH(val) BSP_FLD32(val, 4, 7) |
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114 | #define MLC_TIME_RD_LOW(val) BSP_FLD32(val, 8, 11) |
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115 | #define MLC_TIME_RD_HIGH(val) BSP_FLD32(val, 12, 15) |
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116 | #define MLC_TIME_NAND_TA(val) BSP_FLD32(val, 16, 18) |
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117 | #define MLC_TIME_BUSY_DELAY(val) BSP_FLD32(val, 19, 23) |
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118 | #define MLC_TIME_TCEA_DELAY(val) BSP_FLD32(val, 24, 25) |
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119 | |
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120 | /** @} */ |
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121 | |
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122 | /** |
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123 | * @name MLC NAND Lock Protection Register (MLC_LOCK_PR) |
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124 | * |
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125 | * @{ |
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126 | */ |
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127 | |
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128 | #define MLC_UNLOCK_PROT 0xa25e |
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129 | |
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130 | /** @} */ |
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131 | |
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132 | /** |
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133 | * @name MLC NAND Status Register (MLC_ISR) |
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134 | * |
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135 | * @{ |
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136 | */ |
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137 | |
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138 | #define MLC_ISR_DECODER_FAILURE BSP_BIT32(6) |
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139 | #define MLC_ISR_ERRORS_DETECTED BSP_BIT32(3) |
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140 | #define MLC_ISR_ECC_READY BSP_BIT32(2) |
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141 | #define MLC_ISR_CONTROLLER_READY BSP_BIT32(1) |
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142 | #define MLC_ISR_NAND_READY BSP_BIT32(0) |
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143 | |
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144 | /** @} */ |
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145 | |
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146 | /** |
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147 | * @name MLC NAND Controller Configuration Register (MLC_ICR) |
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148 | * |
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149 | * @{ |
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150 | */ |
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151 | |
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152 | #define MLC_ICR_SOFT_WRITE_PROT BSP_BIT32(3) |
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153 | #define MLC_ICR_LARGE_PAGES BSP_BIT32(2) |
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154 | #define MLC_ICR_ADDR_WORD_COUNT_4_5 BSP_BIT32(1) |
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155 | #define MLC_ICR_IO_BUS_16 BSP_BIT32(0) |
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156 | |
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157 | /** @} */ |
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158 | |
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159 | /** |
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160 | * @name MLC NAND Auto Encode Register (MLC_ECC_AUTO_ENC) |
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161 | * |
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162 | * @{ |
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163 | */ |
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164 | |
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165 | #define MLC_ECC_AUTO_ENC_PROGRAM BSP_BIT32(8) |
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166 | |
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167 | /** @} */ |
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168 | |
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169 | #define MLC_BAD_BLOCK_MASK ((uint32_t) 0xff00) |
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170 | |
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171 | /** |
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172 | * @brief Bad block mark. |
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173 | * |
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174 | * We define our own bad block mark to be able to recognize the blocks that |
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175 | * have been marked bad during operation later. |
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176 | */ |
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177 | #define MLC_BAD_BLOCK_MARK ((uint32_t) 0xbadb) |
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178 | |
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179 | /** |
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180 | * @brief The bytes 4 and 5 are reserved for bad block handling. |
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181 | */ |
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182 | #define MLC_RESERVED ((uint32_t) 0xffff) |
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183 | |
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184 | /** |
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185 | * @name NAND Status Register |
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186 | * |
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187 | * @{ |
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188 | */ |
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189 | |
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190 | #define NAND_STATUS_ERROR (1U << 0) |
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191 | #define NAND_STATUS_READY (1U << 6) |
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192 | #define NAND_STATUS_NOT_PROTECTED (1U << 7) |
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193 | |
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194 | /** @} */ |
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195 | |
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196 | /** |
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197 | * @brief MLC NAND controller configuration. |
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198 | */ |
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199 | typedef struct { |
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200 | uint32_t flags; |
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201 | |
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202 | uint32_t block_count; |
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203 | |
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204 | /** |
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205 | * @brief Value for the MLC NAND Timing Register (MLC_TIME_REG). |
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206 | */ |
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207 | uint32_t time; |
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208 | } lpc32xx_mlc_config; |
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209 | |
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210 | /** |
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211 | * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) |
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212 | * or large pages (2048 Bytes user data and 64 Bytes spare data). |
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213 | */ |
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214 | #define MLC_SMALL_PAGES 0x1U |
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215 | |
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216 | /** |
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217 | * @Brief Selects 3/4 address cycles for small pages/large pages or 4/5 |
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218 | * address cycles. |
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219 | */ |
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220 | #define MLC_MANY_ADDRESS_CYCLES 0x2U |
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221 | |
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222 | /** |
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223 | * @brief Selects 64 or 128 pages per block in case of large pages. |
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224 | */ |
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225 | #define MLC_NORMAL_BLOCKS 0x4U |
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226 | |
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227 | /** |
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228 | * @brief Initializes the MLC NAND controller according to @a cfg. |
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229 | */ |
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230 | void lpc32xx_mlc_init(const lpc32xx_mlc_config *cfg); |
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231 | |
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232 | uint32_t lpc32xx_mlc_page_size(void); |
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233 | |
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234 | uint32_t lpc32xx_mlc_pages_per_block(void); |
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235 | |
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236 | uint32_t lpc32xx_mlc_block_count(void); |
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237 | |
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238 | void lpc32xx_mlc_write_protection( |
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239 | uint32_t page_index_low, |
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240 | uint32_t page_index_high |
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241 | ); |
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242 | |
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243 | void lpc32xx_mlc_read_id(uint8_t *id, size_t n); |
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244 | |
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245 | /** |
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246 | * @brief Reads the page with index @a page_index. |
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247 | * |
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248 | * 32-bit reads will be performed. |
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249 | * |
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250 | * Bytes 7 to 15 of the spare area will contain the ECC. |
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251 | * |
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252 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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253 | * @retval RTEMS_INVALID_ID Invalid @a page_index value. |
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254 | * @retval RTEMS_IO_ERROR Uncorrectable bit error. |
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255 | */ |
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256 | rtems_status_code lpc32xx_mlc_read_page( |
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257 | uint32_t page_index, |
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258 | uint32_t *data, |
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259 | uint32_t *spare |
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260 | ); |
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261 | |
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262 | /** |
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263 | * @brief Erases the block with index @a block_index. |
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264 | * |
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265 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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266 | * @retval RTEMS_INVALID_ID Invalid @a block_index value. |
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267 | * @retval RTEMS_IO_ERROR Erase error. |
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268 | */ |
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269 | rtems_status_code lpc32xx_mlc_erase_block(uint32_t block_index); |
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270 | |
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271 | /** |
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272 | * @brief Erases the block with index @a block_index. |
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273 | * |
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274 | * In case of an erase error all pages and the spare areas of this block are |
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275 | * programmed with zero values. This will mark the first and second page as |
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276 | * bad. |
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277 | * |
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278 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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279 | * @retval RTEMS_INCORRECT_STATE The first or second page of this block is bad. |
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280 | * @retval RTEMS_INVALID_ID Invalid @a block_index value. |
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281 | * @retval RTEMS_IO_ERROR Erase error. |
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282 | */ |
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283 | rtems_status_code lpc32xx_mlc_erase_block_safe(uint32_t block_index); |
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284 | |
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285 | /** |
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286 | * @brief Erases the block with index @a block_index. |
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287 | * |
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288 | * Variant of lpc32xx_mlc_erase_block_safe() with more parameters for |
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289 | * efficiency reasons. The @a page_begin must be the index of the first page |
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290 | * of the block. The @a page_end must be the page index of the last page of |
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291 | * the block plus one. |
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292 | */ |
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293 | rtems_status_code lpc32xx_mlc_erase_block_safe_3( |
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294 | uint32_t block_index, |
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295 | uint32_t page_begin, |
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296 | uint32_t page_end |
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297 | ); |
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298 | |
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299 | /** |
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300 | * @brief Writes zero values to the pages specified by @a page_begin and |
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301 | * @a page_end. |
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302 | * |
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303 | * The data and spare area are cleared to zero. This marks the pages as bad. |
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304 | */ |
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305 | void lpc32xx_mlc_zero_pages(uint32_t page_begin, uint32_t page_end); |
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306 | |
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307 | /** |
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308 | * @brief Writes the page with index @a page_index. |
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309 | * |
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310 | * 32-bit writes will be performed. |
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311 | * |
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312 | * Bytes 7 to 15 of the spare area will be used for the automatically generated |
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313 | * ECC. |
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314 | * |
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315 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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316 | * @retval RTEMS_INVALID_ID Invalid @a page_index value. |
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317 | * @retval RTEMS_IO_ERROR Write error. |
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318 | */ |
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319 | rtems_status_code lpc32xx_mlc_write_page_with_ecc( |
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320 | uint32_t page_index, |
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321 | const uint32_t *data, |
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322 | const uint32_t *spare |
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323 | ); |
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324 | |
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325 | /** |
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326 | * @brief Writes @a src_size Bytes from @a src to the flash area specified by |
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327 | * @a block_begin and @a block_end. |
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328 | * |
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329 | * The @a page_buffer will be used as an intermediate buffer. |
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330 | * |
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331 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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332 | * @retval RTEMS_INVALID_ID Invalid @a block_begin or @a block_end value. |
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333 | * @retval RTEMS_IO_ERROR Too many bad blocks or source area too big. |
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334 | */ |
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335 | rtems_status_code lpc32xx_mlc_write_blocks( |
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336 | uint32_t block_begin, |
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337 | uint32_t block_end, |
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338 | const void *src, |
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339 | size_t src_size, |
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340 | uint32_t page_buffer [MLC_LARGE_DATA_WORD_COUNT] |
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341 | ); |
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342 | |
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343 | /** |
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344 | * @brief Read blocks process function type. |
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345 | * |
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346 | * @see lpc32xx_mlc_read_blocks(). |
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347 | * |
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348 | * @retval false Continue processing. |
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349 | * @retval true Stop processing. |
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350 | */ |
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351 | typedef bool (*lpc32xx_mlc_read_process)( |
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352 | void *process_arg, |
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353 | uint32_t page_index, |
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354 | uint32_t page_size, |
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355 | uint32_t page_data [MLC_LARGE_DATA_WORD_COUNT], |
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356 | uint32_t page_spare [MLC_LARGE_SPARE_WORD_COUNT] |
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357 | ); |
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358 | |
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359 | /** |
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360 | * @brief Reads the pages of block @a block_begin up to and excluding |
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361 | * @a block_end. |
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362 | * |
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363 | * For each page @a process will be called with the @a process_arg parameter, |
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364 | * the page_index, the page data and the page spare. |
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365 | * |
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366 | * The @a page_buffer_0 and @a page_buffer_1 will be used as |
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367 | * intermediate buffers. |
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368 | */ |
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369 | rtems_status_code lpc32xx_mlc_read_blocks( |
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370 | uint32_t block_begin, |
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371 | uint32_t block_end, |
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372 | lpc32xx_mlc_read_process process, |
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373 | void *process_arg, |
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374 | uint32_t page_buffer_0 [MLC_LARGE_DATA_WORD_COUNT], |
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375 | uint32_t page_buffer_1 [MLC_LARGE_DATA_WORD_COUNT] |
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376 | ); |
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377 | |
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378 | static inline bool lpc32xx_mlc_is_bad_page(const uint32_t *spare) |
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379 | { |
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380 | return (spare [1] & MLC_BAD_BLOCK_MASK) != MLC_BAD_BLOCK_MASK; |
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381 | } |
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382 | |
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383 | static inline void lpc32xx_mlc_set_bad_page(uint32_t *spare) |
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384 | { |
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385 | spare [1] = MLC_BAD_BLOCK_MARK; |
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386 | } |
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387 | |
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388 | static inline void lpc32xx_mlc_set_reserved(uint32_t *spare) |
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389 | { |
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390 | spare [1] = MLC_RESERVED; |
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391 | } |
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392 | |
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393 | /** @} */ |
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394 | |
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395 | #ifdef __cplusplus |
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396 | } |
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397 | #endif /* __cplusplus */ |
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398 | |
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399 | #endif /* LIBBSP_ARM_LPC32XX_NAND_MLC_H */ |
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