[3103d4cb] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc32xx_nand_mlc |
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| 5 | * |
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| 6 | * @brief NAND MLC controller API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[03d2108] | 10 | * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * Copyright (c) 2011 Stephan Hoffmann <sho@reLinux.de> |
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[3103d4cb] | 19 | * |
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| 20 | * The license and distribution terms for this file may be |
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| 21 | * found in the file LICENSE in this distribution or at |
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| 22 | * http://www.rtems.com/license/LICENSE. |
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| 23 | */ |
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| 24 | |
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| 25 | #ifndef LIBBSP_ARM_LPC32XX_NAND_MLC_H |
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| 26 | #define LIBBSP_ARM_LPC32XX_NAND_MLC_H |
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| 27 | |
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| 28 | #include <rtems.h> |
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| 29 | |
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| 30 | #include <bsp/utility.h> |
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| 31 | |
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| 32 | #ifdef __cplusplus |
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| 33 | extern "C" { |
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| 34 | #endif /* __cplusplus */ |
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| 35 | |
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| 36 | /** |
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| 37 | * @defgroup lpc32xx_nand_mlc NAND MLC Controller |
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| 38 | * |
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| 39 | * @ingroup lpc32xx |
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| 40 | * |
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| 41 | * @brief NAND MLC Controller. |
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| 42 | * |
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| 43 | * Timing constraints: |
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| 44 | * |
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| 45 | * -# (WR_LOW + 1) / HCLK >= tWP |
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| 46 | * -# (WR_HIGH - WR_LOW) / HCLK >= tWH |
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| 47 | * -# (WR_LOW + 1) / HCLK + (WR_HIGH - WR_LOW) / HCLK >= tWC |
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| 48 | * -# (RD_LOW + 1) / HCLK >= tRP |
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| 49 | * -# (RD_LOW + 1) / HCLK >= tREA + tSU |
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| 50 | * -# (RD_HIGH - RD_LOW) / HCLK >= tREH |
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| 51 | * -# (RD_LOW + 1) / HCLK + (RD_HIGH - RD_LOW) / HCLK >= tRC |
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| 52 | * -# (RD_HIGH - RD_LOW) / HCLK + NAND_TA / HCLK >= tRHZ |
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| 53 | * -# BUSY_DELAY / HCLK >= max(tWB, tRB) |
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| 54 | * -# TCEA_DELAY / HCLK >= tCEA - tREA |
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| 55 | * |
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| 56 | * Known flash layouts (Format: SP = small pages, LP = large pages / address |
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| 57 | * cycles / pages per block): |
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| 58 | * |
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| 59 | * -# SP/3/32 |
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| 60 | * -# SP/4/32 |
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| 61 | * -# LP/4/64 |
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| 62 | * -# LP/5/64 |
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| 63 | * -# LP/5/128 |
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| 64 | * |
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| 65 | * @{ |
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| 66 | */ |
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| 67 | |
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| 68 | /** |
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| 69 | * @name MLC NAND Flash Dimensions |
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| 70 | * |
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| 71 | * @{ |
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| 72 | */ |
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| 73 | |
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| 74 | #define MLC_SMALL_PAGE_SIZE 528 |
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| 75 | #define MLC_SMALL_DATA_SIZE 512 |
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| 76 | #define MLC_SMALL_SPARE_SIZE 16 |
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[82525a75] | 77 | #define MLC_SMALL_USER_SPARE_SIZE 6 |
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| 78 | #define MLC_SMALL_ECC_SPARE_SIZE 10 |
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[3103d4cb] | 79 | #define MLC_SMALL_DATA_WORD_COUNT (MLC_SMALL_DATA_SIZE / 4) |
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| 80 | #define MLC_SMALL_SPARE_WORD_COUNT (MLC_SMALL_SPARE_SIZE / 4) |
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| 81 | #define MLC_SMALL_PAGES_PER_LARGE_PAGE 4 |
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| 82 | #define MLC_LARGE_PAGE_SIZE \ |
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| 83 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_PAGE_SIZE) |
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| 84 | #define MLC_LARGE_DATA_SIZE \ |
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| 85 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_DATA_SIZE) |
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| 86 | #define MLC_LARGE_SPARE_SIZE \ |
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| 87 | (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_SPARE_SIZE) |
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| 88 | #define MLC_LARGE_DATA_WORD_COUNT (MLC_LARGE_DATA_SIZE / 4) |
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| 89 | #define MLC_LARGE_SPARE_WORD_COUNT (MLC_LARGE_SPARE_SIZE / 4) |
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| 90 | |
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| 91 | /** @} */ |
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| 92 | |
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| 93 | /** |
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| 94 | * @name NAND Flash Clock Control Register (FLASHCLK_CTRL) |
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| 95 | * |
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| 96 | * @{ |
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| 97 | */ |
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| 98 | |
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[4a14d7b1] | 99 | #define FLASHCLK_IRQ_MLC BSP_BIT32(5) |
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| 100 | #define FLASHCLK_MLC_DMA_RNB BSP_BIT32(4) |
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| 101 | #define FLASHCLK_MLC_DMA_INT BSP_BIT32(3) |
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| 102 | #define FLASHCLK_SELECT_SLC BSP_BIT32(2) |
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| 103 | #define FLASHCLK_MLC_CLK_ENABLE BSP_BIT32(1) |
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| 104 | #define FLASHCLK_SLC_CLK_ENABLE BSP_BIT32(0) |
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[3103d4cb] | 105 | |
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| 106 | /** @} */ |
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| 107 | |
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| 108 | /** |
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| 109 | * @name MLC NAND Timing Register (MLC_TIME_REG) |
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| 110 | * |
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| 111 | * @{ |
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| 112 | */ |
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| 113 | |
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[4a14d7b1] | 114 | #define MLC_TIME_WR_LOW(val) BSP_FLD32(val, 0, 3) |
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| 115 | #define MLC_TIME_WR_HIGH(val) BSP_FLD32(val, 4, 7) |
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| 116 | #define MLC_TIME_RD_LOW(val) BSP_FLD32(val, 8, 11) |
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| 117 | #define MLC_TIME_RD_HIGH(val) BSP_FLD32(val, 12, 15) |
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| 118 | #define MLC_TIME_NAND_TA(val) BSP_FLD32(val, 16, 18) |
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| 119 | #define MLC_TIME_BUSY_DELAY(val) BSP_FLD32(val, 19, 23) |
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| 120 | #define MLC_TIME_TCEA_DELAY(val) BSP_FLD32(val, 24, 25) |
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[3103d4cb] | 121 | |
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| 122 | /** @} */ |
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| 123 | |
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| 124 | /** |
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| 125 | * @name MLC NAND Lock Protection Register (MLC_LOCK_PR) |
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| 126 | * |
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| 127 | * @{ |
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| 128 | */ |
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| 129 | |
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| 130 | #define MLC_UNLOCK_PROT 0xa25e |
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| 131 | |
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| 132 | /** @} */ |
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| 133 | |
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| 134 | /** |
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| 135 | * @name MLC NAND Status Register (MLC_ISR) |
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| 136 | * |
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| 137 | * @{ |
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| 138 | */ |
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| 139 | |
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[4a14d7b1] | 140 | #define MLC_ISR_DECODER_FAILURE BSP_BIT32(6) |
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[82525a75] | 141 | #define MLC_ISR_SYMBOL_ERRORS(reg) BSP_FLD32GET(reg, 4, 5) |
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[4a14d7b1] | 142 | #define MLC_ISR_ERRORS_DETECTED BSP_BIT32(3) |
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| 143 | #define MLC_ISR_ECC_READY BSP_BIT32(2) |
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| 144 | #define MLC_ISR_CONTROLLER_READY BSP_BIT32(1) |
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| 145 | #define MLC_ISR_NAND_READY BSP_BIT32(0) |
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[3103d4cb] | 146 | |
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| 147 | /** @} */ |
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| 148 | |
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| 149 | /** |
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| 150 | * @name MLC NAND Controller Configuration Register (MLC_ICR) |
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| 151 | * |
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| 152 | * @{ |
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| 153 | */ |
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| 154 | |
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[4a14d7b1] | 155 | #define MLC_ICR_SOFT_WRITE_PROT BSP_BIT32(3) |
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| 156 | #define MLC_ICR_LARGE_PAGES BSP_BIT32(2) |
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| 157 | #define MLC_ICR_ADDR_WORD_COUNT_4_5 BSP_BIT32(1) |
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| 158 | #define MLC_ICR_IO_BUS_16 BSP_BIT32(0) |
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[3103d4cb] | 159 | |
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| 160 | /** @} */ |
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| 161 | |
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| 162 | /** |
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| 163 | * @name MLC NAND Auto Encode Register (MLC_ECC_AUTO_ENC) |
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| 164 | * |
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| 165 | * @{ |
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| 166 | */ |
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| 167 | |
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[4a14d7b1] | 168 | #define MLC_ECC_AUTO_ENC_PROGRAM BSP_BIT32(8) |
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[3103d4cb] | 169 | |
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| 170 | /** @} */ |
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| 171 | |
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| 172 | /** |
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| 173 | * @name NAND Status Register |
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| 174 | * |
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| 175 | * @{ |
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| 176 | */ |
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| 177 | |
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| 178 | #define NAND_STATUS_ERROR (1U << 0) |
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| 179 | #define NAND_STATUS_READY (1U << 6) |
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| 180 | #define NAND_STATUS_NOT_PROTECTED (1U << 7) |
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| 181 | |
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| 182 | /** @} */ |
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| 183 | |
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| 184 | /** |
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| 185 | * @brief MLC NAND controller configuration. |
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| 186 | */ |
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| 187 | typedef struct { |
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[f437107] | 188 | uint32_t flags; |
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[3103d4cb] | 189 | |
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| 190 | uint32_t block_count; |
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| 191 | |
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| 192 | /** |
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| 193 | * @brief Value for the MLC NAND Timing Register (MLC_TIME_REG). |
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| 194 | */ |
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| 195 | uint32_t time; |
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| 196 | } lpc32xx_mlc_config; |
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| 197 | |
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[f437107] | 198 | /** |
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| 199 | * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) |
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[82525a75] | 200 | * or large pages (2048 Bytes user data and 64 Bytes spare data) if not set. |
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[f437107] | 201 | */ |
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| 202 | #define MLC_SMALL_PAGES 0x1U |
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| 203 | |
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| 204 | /** |
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[82525a75] | 205 | * @Brief Selects 4/5 address cycles for small/large pages or 3/4 address |
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| 206 | * cycles if not set. |
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[f437107] | 207 | */ |
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| 208 | #define MLC_MANY_ADDRESS_CYCLES 0x2U |
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| 209 | |
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| 210 | /** |
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[82525a75] | 211 | * @brief Selects 64 pages per block or 128 pages per block if not set. |
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| 212 | * |
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| 213 | * This flag is only valid for large pages. |
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[f437107] | 214 | */ |
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| 215 | #define MLC_NORMAL_BLOCKS 0x4U |
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| 216 | |
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[82525a75] | 217 | /** |
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| 218 | * @brief Selects 16-bit IO width or 8-bit IO width if not set. |
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| 219 | */ |
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| 220 | #define MLC_IO_WIDTH_16_BIT 0x8U |
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| 221 | |
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[3103d4cb] | 222 | /** |
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| 223 | * @brief Initializes the MLC NAND controller according to @a cfg. |
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| 224 | */ |
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| 225 | void lpc32xx_mlc_init(const lpc32xx_mlc_config *cfg); |
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| 226 | |
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| 227 | uint32_t lpc32xx_mlc_page_size(void); |
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| 228 | |
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| 229 | uint32_t lpc32xx_mlc_pages_per_block(void); |
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| 230 | |
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| 231 | uint32_t lpc32xx_mlc_block_count(void); |
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| 232 | |
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[82525a75] | 233 | uint32_t lpc32xx_mlc_io_width(void); |
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| 234 | |
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[3103d4cb] | 235 | void lpc32xx_mlc_write_protection( |
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| 236 | uint32_t page_index_low, |
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| 237 | uint32_t page_index_high |
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| 238 | ); |
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| 239 | |
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| 240 | void lpc32xx_mlc_read_id(uint8_t *id, size_t n); |
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| 241 | |
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| 242 | /** |
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| 243 | * @brief Reads the page with index @a page_index. |
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| 244 | * |
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[82525a75] | 245 | * Bytes 6 to 15 of the spare area will contain the ECC. |
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[3103d4cb] | 246 | * |
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[82525a75] | 247 | * If the read is successful, then the @a symbol_error_count will contain the |
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| 248 | * number of detected symbol errors (0, 1, 2, 3, or 4), else the value will be |
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| 249 | * 0xffffffff. The @a symbol_error_count pointer may be @c NULL. |
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[3103d4cb] | 250 | * |
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| 251 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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| 252 | * @retval RTEMS_INVALID_ID Invalid @a page_index value. |
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| 253 | * @retval RTEMS_IO_ERROR Uncorrectable bit error. |
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| 254 | */ |
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| 255 | rtems_status_code lpc32xx_mlc_read_page( |
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| 256 | uint32_t page_index, |
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[82525a75] | 257 | void *data, |
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| 258 | void *spare, |
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| 259 | uint32_t *symbol_error_count |
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[3103d4cb] | 260 | ); |
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| 261 | |
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[82525a75] | 262 | /** |
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| 263 | * @brief Checks if the block with index @a block_index is valid. |
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| 264 | * |
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| 265 | * The initial valid block information of the manufacturer will be used. |
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[8d8f363] | 266 | * Unfortunately there seems to be no standard for this. A block will be |
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[82525a75] | 267 | * considered as bad if the first or second page of this block does not contain |
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| 268 | * 0xff at the 6th byte of the spare area. This should work for flashes with |
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| 269 | * small pages and a 8-bit IO width. |
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| 270 | * |
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| 271 | * @retval RTEMS_SUCCESSFUL The block is valid. |
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| 272 | * @retval RTEMS_INVALID_ID Invalid @a block_index value. |
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| 273 | * @retval RTEMS_IO_ERROR Uncorrectable bit error. |
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| 274 | * @retval RTEMS_INCORRECT_STATE The block is bad. |
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| 275 | * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash |
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| 276 | * type. |
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| 277 | */ |
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| 278 | rtems_status_code lpc32xx_mlc_is_valid_block(uint32_t block_index); |
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| 279 | |
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[3103d4cb] | 280 | /** |
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| 281 | * @brief Erases the block with index @a block_index. |
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| 282 | * |
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| 283 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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| 284 | * @retval RTEMS_INVALID_ID Invalid @a block_index value. |
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[82525a75] | 285 | * @retval RTEMS_UNSATISFIED Erase error. |
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[3103d4cb] | 286 | */ |
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| 287 | rtems_status_code lpc32xx_mlc_erase_block(uint32_t block_index); |
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| 288 | |
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[03d2108] | 289 | /** |
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| 290 | * @brief Erases the block with index @a block_index. |
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| 291 | * |
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| 292 | * In case of an erase error all pages and the spare areas of this block are |
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[82525a75] | 293 | * programmed with zero values. This will hopefully mark the block as bad. |
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[03d2108] | 294 | * |
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| 295 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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[82525a75] | 296 | * @retval RTEMS_INCORRECT_STATE The block is bad. |
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[03d2108] | 297 | * @retval RTEMS_INVALID_ID Invalid @a block_index value. |
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[82525a75] | 298 | * @retval RTEMS_UNSATISFIED Erase error. |
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| 299 | * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash |
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| 300 | * type. |
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[03d2108] | 301 | */ |
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| 302 | rtems_status_code lpc32xx_mlc_erase_block_safe(uint32_t block_index); |
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| 303 | |
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| 304 | /** |
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| 305 | * @brief Erases the block with index @a block_index. |
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| 306 | * |
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| 307 | * Variant of lpc32xx_mlc_erase_block_safe() with more parameters for |
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[542d350e] | 308 | * efficiency reasons. The @a page_begin must be the index of the first page |
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| 309 | * of the block. The @a page_end must be the page index of the last page of |
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| 310 | * the block plus one. |
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[03d2108] | 311 | */ |
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| 312 | rtems_status_code lpc32xx_mlc_erase_block_safe_3( |
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| 313 | uint32_t block_index, |
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[542d350e] | 314 | uint32_t page_begin, |
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| 315 | uint32_t page_end |
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[03d2108] | 316 | ); |
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| 317 | |
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[542d350e] | 318 | /** |
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| 319 | * @brief Writes zero values to the pages specified by @a page_begin and |
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| 320 | * @a page_end. |
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| 321 | * |
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| 322 | * The data and spare area are cleared to zero. This marks the pages as bad. |
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| 323 | */ |
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| 324 | void lpc32xx_mlc_zero_pages(uint32_t page_begin, uint32_t page_end); |
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| 325 | |
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[3103d4cb] | 326 | /** |
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| 327 | * @brief Writes the page with index @a page_index. |
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| 328 | * |
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[82525a75] | 329 | * Only the bytes 0 to 5 of the spare area can be used for user data, the bytes |
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| 330 | * 6 to 15 will be used for the automatically generated ECC. |
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[3103d4cb] | 331 | * |
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| 332 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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| 333 | * @retval RTEMS_INVALID_ID Invalid @a page_index value. |
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| 334 | * @retval RTEMS_IO_ERROR Write error. |
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| 335 | */ |
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| 336 | rtems_status_code lpc32xx_mlc_write_page_with_ecc( |
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| 337 | uint32_t page_index, |
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[82525a75] | 338 | const void *data, |
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| 339 | const void *spare |
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[3103d4cb] | 340 | ); |
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| 341 | |
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| 342 | /** |
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| 343 | * @brief Writes @a src_size Bytes from @a src to the flash area specified by |
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| 344 | * @a block_begin and @a block_end. |
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| 345 | * |
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| 346 | * The @a page_buffer will be used as an intermediate buffer. |
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| 347 | * |
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| 348 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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| 349 | * @retval RTEMS_INVALID_ID Invalid @a block_begin or @a block_end value. |
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[03d2108] | 350 | * @retval RTEMS_IO_ERROR Too many bad blocks or source area too big. |
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[3103d4cb] | 351 | */ |
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| 352 | rtems_status_code lpc32xx_mlc_write_blocks( |
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| 353 | uint32_t block_begin, |
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| 354 | uint32_t block_end, |
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| 355 | const void *src, |
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| 356 | size_t src_size, |
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| 357 | uint32_t page_buffer [MLC_LARGE_DATA_WORD_COUNT] |
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| 358 | ); |
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| 359 | |
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| 360 | /** |
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| 361 | * @brief Read blocks process function type. |
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| 362 | * |
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| 363 | * @see lpc32xx_mlc_read_blocks(). |
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| 364 | * |
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| 365 | * @retval false Continue processing. |
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| 366 | * @retval true Stop processing. |
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| 367 | */ |
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| 368 | typedef bool (*lpc32xx_mlc_read_process)( |
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| 369 | void *process_arg, |
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| 370 | uint32_t page_index, |
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| 371 | uint32_t page_size, |
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| 372 | uint32_t page_data [MLC_LARGE_DATA_WORD_COUNT], |
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| 373 | uint32_t page_spare [MLC_LARGE_SPARE_WORD_COUNT] |
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| 374 | ); |
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| 375 | |
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| 376 | /** |
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| 377 | * @brief Reads the pages of block @a block_begin up to and excluding |
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| 378 | * @a block_end. |
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| 379 | * |
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| 380 | * For each page @a process will be called with the @a process_arg parameter, |
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| 381 | * the page_index, the page data and the page spare. |
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| 382 | * |
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| 383 | * The @a page_buffer_0 and @a page_buffer_1 will be used as |
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| 384 | * intermediate buffers. |
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| 385 | */ |
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| 386 | rtems_status_code lpc32xx_mlc_read_blocks( |
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| 387 | uint32_t block_begin, |
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| 388 | uint32_t block_end, |
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| 389 | lpc32xx_mlc_read_process process, |
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| 390 | void *process_arg, |
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| 391 | uint32_t page_buffer_0 [MLC_LARGE_DATA_WORD_COUNT], |
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| 392 | uint32_t page_buffer_1 [MLC_LARGE_DATA_WORD_COUNT] |
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| 393 | ); |
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| 394 | |
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[f41fb2b] | 395 | /** |
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| 396 | * @brief Checks if the page spare area indicates to a bad page. |
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| 397 | * |
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| 398 | * If the first (byte offset 0) or sixth (byte offset 5) byte of the spare area |
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| 399 | * has a value other than 0xff, then it returns @true (the page is bad), else |
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| 400 | * it returns @a false (the page is not bad). |
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| 401 | * |
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| 402 | * Samsung uses the sixth byte to indicate a bad page. Mircon uses the first |
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| 403 | * and sixth byte to indicate a bad page. |
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| 404 | * |
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| 405 | * This functions works only for small page flashes. |
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| 406 | */ |
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[3103d4cb] | 407 | static inline bool lpc32xx_mlc_is_bad_page(const uint32_t *spare) |
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| 408 | { |
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[f41fb2b] | 409 | uint32_t first_byte_mask = 0x000000ff; |
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| 410 | uint32_t sixth_byte_mask = 0x0000ff00; |
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| 411 | |
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| 412 | return (spare [0] & first_byte_mask) != first_byte_mask |
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| 413 | || (spare [1] & sixth_byte_mask) != sixth_byte_mask; |
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[03d2108] | 414 | } |
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| 415 | |
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[3103d4cb] | 416 | /** @} */ |
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| 417 | |
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| 418 | #ifdef __cplusplus |
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| 419 | } |
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| 420 | #endif /* __cplusplus */ |
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| 421 | |
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| 422 | #endif /* LIBBSP_ARM_LPC32XX_NAND_MLC_H */ |
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