| 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc32xx_reg |
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| 5 | * |
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| 6 | * @brief Register base addresses. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2009 |
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| 11 | * embedded brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * <rtems@embedded-brains.de> |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * http: |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H |
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| 23 | #define LIBBSP_ARM_LPC32XX_LPC32XX_H |
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| 24 | |
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| 25 | #include <stdint.h> |
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| 26 | |
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| 27 | #include <bsp/utility.h> |
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| 28 | |
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| 29 | /** |
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| 30 | * @defgroup lpc32xx_reg Register Definitions |
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| 31 | * |
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| 32 | * @ingroup lpc32xx |
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| 33 | * |
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| 34 | * @brief Register definitions. |
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| 35 | * |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |
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| 39 | /** |
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| 40 | * @name Register Base Addresses |
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| 41 | * |
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| 42 | * @{ |
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| 43 | */ |
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| 44 | |
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| 45 | #define LPC32XX_BASE_ADC 0x40048000 |
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| 46 | #define LPC32XX_BASE_SYSCON 0x40004000 |
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| 47 | #define LPC32XX_BASE_DEBUG_CTRL 0x40040000 |
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| 48 | #define LPC32XX_BASE_DMA 0x31000000 |
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| 49 | #define LPC32XX_BASE_EMC 0x31080000 |
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| 50 | #define LPC32XX_BASE_EMC_CS_0 0xe0000000 |
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| 51 | #define LPC32XX_BASE_EMC_CS_1 0xe1000000 |
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| 52 | #define LPC32XX_BASE_EMC_CS_2 0xe2000000 |
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| 53 | #define LPC32XX_BASE_EMC_CS_3 0xe3000000 |
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| 54 | #define LPC32XX_BASE_EMC_DYCS_0 0x80000000 |
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| 55 | #define LPC32XX_BASE_EMC_DYCS_1 0xa0000000 |
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| 56 | #define LPC32XX_BASE_ETB_CFG 0x310c0000 |
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| 57 | #define LPC32XX_BASE_ETB_DATA 0x310e0000 |
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| 58 | #define LPC32XX_BASE_ETHERNET 0x31060000 |
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| 59 | #define LPC32XX_BASE_GPIO 0x40028000 |
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| 60 | #define LPC32XX_BASE_I2C_1 0x400a0000 |
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| 61 | #define LPC32XX_BASE_I2C_2 0x400a8000 |
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| 62 | #define LPC32XX_BASE_I2S_0 0x20094000 |
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| 63 | #define LPC32XX_BASE_I2S_1 0x2009c000 |
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| 64 | #define LPC32XX_BASE_IRAM 0x08000000 |
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| 65 | #define LPC32XX_BASE_IROM 0x0c000000 |
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| 66 | #define LPC32XX_BASE_KEYSCAN 0x40050000 |
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| 67 | #define LPC32XX_BASE_LCD 0x31040000 |
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| 68 | #define LPC32XX_BASE_MCPWM 0x400e8000 |
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| 69 | #define LPC32XX_BASE_MIC 0x40008000 |
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| 70 | #define LPC32XX_BASE_NAND_MLC 0x200a8000 |
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| 71 | #define LPC32XX_BASE_NAND_SLC 0x20020000 |
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| 72 | #define LPC32XX_BASE_PWM_1 0x4005c000 |
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| 73 | #define LPC32XX_BASE_PWM_2 0x4005c004 |
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| 74 | #define LPC32XX_BASE_PWM_3 0x4002c000 |
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| 75 | #define LPC32XX_BASE_PWM_4 0x40030000 |
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| 76 | #define LPC32XX_BASE_RTC 0x40024000 |
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| 77 | #define LPC32XX_BASE_RTC_RAM 0x40024080 |
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| 78 | #define LPC32XX_BASE_SDCARD 0x20098000 |
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| 79 | #define LPC32XX_BASE_SIC_1 0x4000c000 |
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| 80 | #define LPC32XX_BASE_SIC_2 0x40010000 |
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| 81 | #define LPC32XX_BASE_SPI_1 0x20088000 |
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| 82 | #define LPC32XX_BASE_SPI_2 0x20090000 |
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| 83 | #define LPC32XX_BASE_SSP_0 0x20084000 |
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| 84 | #define LPC32XX_BASE_SSP_1 0x2008c000 |
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| 85 | #define LPC32XX_BASE_TIMER_0 0x40044000 |
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| 86 | #define LPC32XX_BASE_TIMER_1 0x4004c000 |
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| 87 | #define LPC32XX_BASE_TIMER_2 0x40058000 |
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| 88 | #define LPC32XX_BASE_TIMER_3 0x40060000 |
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| 89 | #define LPC32XX_BASE_TIMER_5 0x4002c000 |
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| 90 | #define LPC32XX_BASE_TIMER_6 0x40030000 |
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| 91 | #define LPC32XX_BASE_TIMER_HS 0x40038000 |
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| 92 | #define LPC32XX_BASE_TIMER_MS 0x40034000 |
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| 93 | #define LPC32XX_BASE_UART_1 0x40014000 |
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| 94 | #define LPC32XX_BASE_UART_2 0x40018000 |
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| 95 | #define LPC32XX_BASE_UART_3 0x40080000 |
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| 96 | #define LPC32XX_BASE_UART_4 0x40088000 |
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| 97 | #define LPC32XX_BASE_UART_5 0x40090000 |
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| 98 | #define LPC32XX_BASE_UART_6 0x40098000 |
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| 99 | #define LPC32XX_BASE_UART_7 0x4001c000 |
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| 100 | #define LPC32XX_BASE_USB 0x31020000 |
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| 101 | #define LPC32XX_BASE_USB_OTG_I2C 0x31020300 |
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| 102 | #define LPC32XX_BASE_WDT 0x4003c000 |
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| 103 | |
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| 104 | /** @} */ |
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| 105 | |
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| 106 | /** |
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| 107 | * @name Miscanellanous Registers |
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| 108 | * |
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| 109 | * @{ |
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| 110 | */ |
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| 111 | |
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| 112 | #define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0) |
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| 113 | #define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4) |
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| 114 | #define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8) |
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| 115 | #define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc) |
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| 116 | #define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0) |
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| 117 | #define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000) |
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| 118 | #define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004) |
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| 119 | #define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008) |
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| 120 | #define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8) |
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| 121 | #define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090) |
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| 122 | #define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c) |
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| 123 | #define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4) |
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| 124 | #define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8) |
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| 125 | #define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110) |
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| 126 | #define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300) |
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| 127 | #define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300) |
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| 128 | #define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304) |
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| 129 | #define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308) |
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| 130 | #define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c) |
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| 131 | #define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310) |
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| 132 | #define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044) |
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| 133 | #define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c) |
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| 134 | #define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050) |
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| 135 | #define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048) |
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| 136 | #define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058) |
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| 137 | #define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040) |
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| 138 | #define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4) |
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| 139 | #define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec) |
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| 140 | #define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030) |
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| 141 | #define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020) |
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| 142 | #define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018) |
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| 143 | #define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038) |
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| 144 | #define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028) |
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| 145 | #define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034) |
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| 146 | #define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024) |
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| 147 | #define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c) |
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| 148 | #define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c) |
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| 149 | #define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064) |
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| 150 | #define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c) |
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| 151 | #define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080) |
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| 152 | #define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8) |
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| 153 | #define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8) |
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| 154 | #define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090) |
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| 155 | #define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054) |
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| 156 | #define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c) |
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| 157 | #define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078) |
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| 158 | #define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4) |
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| 159 | #define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac) |
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| 160 | #define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0) |
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| 161 | #define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc) |
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| 162 | #define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4) |
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| 163 | #define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060) |
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| 164 | #define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0) |
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| 165 | #define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8) |
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| 166 | #define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4) |
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| 167 | #define LPC32XX_POS0_IRAM_CTRl (*(volatile uint32_t *) 0x40004110) |
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| 168 | #define LPC32XX_POS1_IRAM_CTRl (*(volatile uint32_t *) 0x40004114) |
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| 169 | |
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| 170 | /** @} */ |
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| 171 | |
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| 172 | /** |
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| 173 | * @name GPIO Registers |
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| 174 | * |
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| 175 | * @{ |
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| 176 | */ |
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| 177 | |
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| 178 | #define LPC32XX_P0_INP_STATE (*(volatile uint32_t *) 0x40028040) |
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| 179 | #define LPC32XX_P0_OUTP_SET (*(volatile uint32_t *) 0x40028044) |
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| 180 | #define LPC32XX_P0_OUTP_CLR (*(volatile uint32_t *) 0x40028048) |
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| 181 | #define LPC32XX_P0_DIR_SET (*(volatile uint32_t *) 0x40028050) |
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| 182 | #define LPC32XX_P0_DIR_CLR (*(volatile uint32_t *) 0x40028054) |
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| 183 | #define LPC32XX_P0_DIR_STATE (*(volatile uint32_t *) 0x40028058) |
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| 184 | #define LPC32XX_P0_OUTP_STATE (*(volatile uint32_t *) 0x4002804c) |
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| 185 | #define LPC32XX_P1_INP_STATE (*(volatile uint32_t *) 0x40028060) |
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| 186 | #define LPC32XX_P1_OUTP_SET (*(volatile uint32_t *) 0x40028064) |
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| 187 | #define LPC32XX_P1_OUTP_CLR (*(volatile uint32_t *) 0x40028068) |
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| 188 | #define LPC32XX_P1_DIR_SET (*(volatile uint32_t *) 0x40028070) |
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| 189 | #define LPC32XX_P1_DIR_CLR (*(volatile uint32_t *) 0x40028074) |
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| 190 | #define LPC32XX_P1_DIR_STATE (*(volatile uint32_t *) 0x40028078) |
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| 191 | #define LPC32XX_P1_OUTP_STATE (*(volatile uint32_t *) 0x4002806c) |
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| 192 | #define LPC32XX_P2_INP_STATE (*(volatile uint32_t *) 0x4002801c) |
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| 193 | #define LPC32XX_P2_OUTP_SET (*(volatile uint32_t *) 0x40028020) |
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| 194 | #define LPC32XX_P2_OUTP_CLR (*(volatile uint32_t *) 0x40028024) |
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| 195 | #define LPC32XX_P2_DIR_SET (*(volatile uint32_t *) 0x40028010) |
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| 196 | #define LPC32XX_P2_DIR_CLR (*(volatile uint32_t *) 0x40028014) |
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| 197 | #define LPC32XX_P2_DIR_STATE (*(volatile uint32_t *) 0x40028018) |
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| 198 | #define LPC32XX_P3_INP_STATE (*(volatile uint32_t *) 0x40028000) |
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| 199 | #define LPC32XX_P3_OUTP_SET (*(volatile uint32_t *) 0x40028004) |
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| 200 | #define LPC32XX_P3_OUTP_CLR (*(volatile uint32_t *) 0x40028008) |
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| 201 | #define LPC32XX_P3_OUTP_STATE (*(volatile uint32_t *) 0x4002800c) |
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| 202 | |
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| 203 | /** @} */ |
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| 204 | |
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| 205 | /** |
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| 206 | * @name Power Control Register (PWR_CTRL) |
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| 207 | * |
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| 208 | * @{ |
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| 209 | */ |
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| 210 | |
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| 211 | #define PWR_STOP BIT32(0) |
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| 212 | #define PWR_HIGHCORE_ALWAYS BIT32(1) |
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| 213 | #define PWR_NORMAL_RUN_MODE BIT32(2) |
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| 214 | #define PWR_SYSCLKEN_ALWAYS BIT32(3) |
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| 215 | #define PWR_SYSCLKEN_HIGH BIT32(4) |
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| 216 | #define PWR_HIGHCORE_HIGH BIT32(5) |
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| 217 | #define PWR_SDRAM_AUTO_REFRESH BIT32(7) |
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| 218 | #define PWR_UPDATE_EMCSREFREQ BIT32(8) |
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| 219 | #define PWR_EMCSREFREQ BIT32(9) |
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| 220 | #define PWR_HCLK_USES_PERIPH_CLK BIT32(10) |
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| 221 | |
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| 222 | /** @} */ |
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| 223 | |
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| 224 | /** |
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| 225 | * @name HCLK PLL Control Register (HCLKPLL_CTRL) |
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| 226 | * |
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| 227 | * @{ |
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| 228 | */ |
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| 229 | |
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| 230 | #define HCLK_PLL_LOCK BIT32(0) |
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| 231 | #define HCLK_PLL_M(val) FIELD32(val, 1, 8) |
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| 232 | #define HCLK_PLL_N(val) FIELD32(val, 9, 2) |
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| 233 | #define HCLK_PLL_P(val) FIELD32(val, 11, 2) |
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| 234 | #define HCLK_PLL_FBD_FCLKOUT BIT32(13) |
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| 235 | #define HCLK_PLL_DIRECT BIT32(14) |
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| 236 | #define HCLK_PLL_BYPASS BIT32(15) |
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| 237 | #define HCLK_PLL_POWER BIT32(16) |
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| 238 | |
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| 239 | /** @} */ |
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| 240 | |
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| 241 | /** |
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| 242 | * @name HCLK Divider Control Register (HCLKDIV_CTRL) |
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| 243 | * |
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| 244 | * @{ |
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| 245 | */ |
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| 246 | |
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| 247 | #define HCLK_DIV_HCLK(val) FIELD32(val, 0, 2) |
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| 248 | #define HCLK_DIV_PERIPH_CLK(val) FIELD32(val, 2, 5) |
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| 249 | #define HCLK_DIV_DDRAM_CLK(val) FIELD32(val, 7, 2) |
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| 250 | |
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| 251 | /** @} */ |
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| 252 | |
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| 253 | /** @} */ |
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| 254 | |
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| 255 | #endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */ |
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