1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_reg |
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5 | * |
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6 | * @brief Register base addresses. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009, 2010 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http: |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H |
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23 | #define LIBBSP_ARM_LPC32XX_LPC32XX_H |
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24 | |
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25 | #include <stdint.h> |
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26 | |
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27 | #include <bsp/utility.h> |
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28 | #include <bsp/lpc-timer.h> |
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29 | #include <bsp/lpc-dma.h> |
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30 | #include <bsp/lpc-i2s.h> |
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31 | #include <bsp/lpc-emc.h> |
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32 | |
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33 | /** |
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34 | * @defgroup lpc32xx_reg Register Definitions |
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35 | * |
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36 | * @ingroup lpc32xx |
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37 | * |
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38 | * @brief Register definitions. |
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39 | * |
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40 | * @{ |
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41 | */ |
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42 | |
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43 | /** |
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44 | * @name Register Base Addresses |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | #define LPC32XX_BASE_ADC 0x40048000 |
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50 | #define LPC32XX_BASE_SYSCON 0x40004000 |
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51 | #define LPC32XX_BASE_DEBUG_CTRL 0x40040000 |
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52 | #define LPC32XX_BASE_DMA 0x31000000 |
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53 | #define LPC32XX_BASE_EMC 0x31080000 |
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54 | #define LPC32XX_BASE_EMC_CS_0 0xe0000000 |
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55 | #define LPC32XX_BASE_EMC_CS_1 0xe1000000 |
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56 | #define LPC32XX_BASE_EMC_CS_2 0xe2000000 |
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57 | #define LPC32XX_BASE_EMC_CS_3 0xe3000000 |
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58 | #define LPC32XX_BASE_EMC_DYCS_0 0x80000000 |
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59 | #define LPC32XX_BASE_EMC_DYCS_1 0xa0000000 |
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60 | #define LPC32XX_BASE_ETB_CFG 0x310c0000 |
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61 | #define LPC32XX_BASE_ETB_DATA 0x310e0000 |
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62 | #define LPC32XX_BASE_ETHERNET 0x31060000 |
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63 | #define LPC32XX_BASE_GPIO 0x40028000 |
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64 | #define LPC32XX_BASE_I2C_1 0x400a0000 |
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65 | #define LPC32XX_BASE_I2C_2 0x400a8000 |
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66 | #define LPC32XX_BASE_I2S_0 0x20094000 |
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67 | #define LPC32XX_BASE_I2S_1 0x2009c000 |
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68 | #define LPC32XX_BASE_IRAM 0x08000000 |
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69 | #define LPC32XX_BASE_IROM 0x0c000000 |
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70 | #define LPC32XX_BASE_KEYSCAN 0x40050000 |
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71 | #define LPC32XX_BASE_LCD 0x31040000 |
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72 | #define LPC32XX_BASE_MCPWM 0x400e8000 |
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73 | #define LPC32XX_BASE_MIC 0x40008000 |
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74 | #define LPC32XX_BASE_NAND_MLC 0x200a8000 |
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75 | #define LPC32XX_BASE_NAND_SLC 0x20020000 |
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76 | #define LPC32XX_BASE_PWM_1 0x4005c000 |
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77 | #define LPC32XX_BASE_PWM_2 0x4005c004 |
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78 | #define LPC32XX_BASE_PWM_3 0x4002c000 |
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79 | #define LPC32XX_BASE_PWM_4 0x40030000 |
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80 | #define LPC32XX_BASE_RTC 0x40024000 |
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81 | #define LPC32XX_BASE_RTC_RAM 0x40024080 |
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82 | #define LPC32XX_BASE_SDCARD 0x20098000 |
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83 | #define LPC32XX_BASE_SIC_1 0x4000c000 |
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84 | #define LPC32XX_BASE_SIC_2 0x40010000 |
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85 | #define LPC32XX_BASE_SPI_1 0x20088000 |
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86 | #define LPC32XX_BASE_SPI_2 0x20090000 |
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87 | #define LPC32XX_BASE_SSP_0 0x20084000 |
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88 | #define LPC32XX_BASE_SSP_1 0x2008c000 |
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89 | #define LPC32XX_BASE_TIMER_0 0x40044000 |
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90 | #define LPC32XX_BASE_TIMER_1 0x4004c000 |
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91 | #define LPC32XX_BASE_TIMER_2 0x40058000 |
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92 | #define LPC32XX_BASE_TIMER_3 0x40060000 |
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93 | #define LPC32XX_BASE_TIMER_5 0x4002c000 |
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94 | #define LPC32XX_BASE_TIMER_6 0x40030000 |
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95 | #define LPC32XX_BASE_TIMER_HS 0x40038000 |
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96 | #define LPC32XX_BASE_TIMER_MS 0x40034000 |
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97 | #define LPC32XX_BASE_UART_1 0x40014000 |
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98 | #define LPC32XX_BASE_UART_2 0x40018000 |
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99 | #define LPC32XX_BASE_UART_3 0x40080000 |
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100 | #define LPC32XX_BASE_UART_4 0x40088000 |
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101 | #define LPC32XX_BASE_UART_5 0x40090000 |
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102 | #define LPC32XX_BASE_UART_6 0x40098000 |
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103 | #define LPC32XX_BASE_UART_7 0x4001c000 |
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104 | #define LPC32XX_BASE_USB 0x31020000 |
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105 | #define LPC32XX_BASE_USB_OTG_I2C 0x31020300 |
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106 | #define LPC32XX_BASE_WDT 0x4003c000 |
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107 | |
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108 | /** @} */ |
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109 | |
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110 | /** |
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111 | * @name Miscanellanous Registers |
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112 | * |
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113 | * @{ |
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114 | */ |
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115 | |
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116 | #define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0) |
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117 | #define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4) |
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118 | #define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8) |
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119 | #define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc) |
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120 | #define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0) |
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121 | #define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000) |
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122 | #define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004) |
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123 | #define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008) |
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124 | #define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8) |
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125 | #define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090) |
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126 | #define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c) |
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127 | #define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4) |
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128 | #define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8) |
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129 | #define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110) |
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130 | #define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300) |
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131 | #define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300) |
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132 | #define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304) |
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133 | #define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308) |
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134 | #define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c) |
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135 | #define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310) |
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136 | #define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044) |
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137 | #define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c) |
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138 | #define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050) |
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139 | #define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048) |
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140 | #define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058) |
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141 | #define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040) |
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142 | #define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4) |
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143 | #define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec) |
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144 | #define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030) |
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145 | #define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020) |
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146 | #define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018) |
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147 | #define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038) |
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148 | #define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028) |
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149 | #define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034) |
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150 | #define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024) |
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151 | #define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c) |
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152 | #define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c) |
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153 | #define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064) |
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154 | #define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c) |
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155 | #define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080) |
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156 | #define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8) |
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157 | #define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8) |
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158 | #define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090) |
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159 | #define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054) |
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160 | #define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c) |
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161 | #define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078) |
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162 | #define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4) |
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163 | #define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac) |
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164 | #define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0) |
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165 | #define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc) |
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166 | #define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4) |
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167 | #define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060) |
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168 | #define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0) |
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169 | #define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8) |
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170 | #define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4) |
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171 | #define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110) |
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172 | #define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114) |
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173 | #define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068) |
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174 | |
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175 | /** @} */ |
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176 | |
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177 | /** |
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178 | * @name Power Control Register (PWR_CTRL) |
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179 | * |
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180 | * @{ |
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181 | */ |
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182 | |
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183 | #define PWR_STOP BSP_BIT32(0) |
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184 | #define PWR_HIGHCORE_ALWAYS BSP_BIT32(1) |
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185 | #define PWR_NORMAL_RUN_MODE BSP_BIT32(2) |
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186 | #define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3) |
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187 | #define PWR_SYSCLKEN_HIGH BSP_BIT32(4) |
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188 | #define PWR_HIGHCORE_HIGH BSP_BIT32(5) |
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189 | #define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7) |
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190 | #define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8) |
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191 | #define PWR_EMCSREFREQ BSP_BIT32(9) |
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192 | #define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10) |
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193 | |
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194 | /** @} */ |
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195 | |
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196 | /** |
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197 | * @name HCLK PLL Control Register (HCLKPLL_CTRL) |
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198 | * |
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199 | * @{ |
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200 | */ |
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201 | |
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202 | #define HCLK_PLL_LOCK BSP_BIT32(0) |
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203 | #define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8) |
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204 | #define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10) |
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205 | #define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12) |
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206 | #define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13) |
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207 | #define HCLK_PLL_DIRECT BSP_BIT32(14) |
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208 | #define HCLK_PLL_BYPASS BSP_BIT32(15) |
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209 | #define HCLK_PLL_POWER BSP_BIT32(16) |
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210 | |
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211 | /** @} */ |
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212 | |
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213 | /** |
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214 | * @name HCLK Divider Control Register (HCLKDIV_CTRL) |
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215 | * |
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216 | * @{ |
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217 | */ |
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218 | |
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219 | #define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1) |
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220 | #define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6) |
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221 | #define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8) |
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222 | |
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223 | /** @} */ |
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224 | |
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225 | /** |
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226 | * @name Timer Clock Control Register (TIMCLK_CTRL) |
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227 | * |
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228 | * @{ |
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229 | */ |
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230 | |
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231 | #define TIMCLK_CTRL_WDT BSP_BIT32(0) |
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232 | #define TIMCLK_CTRL_HST BSP_BIT32(1) |
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233 | |
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234 | /** @} */ |
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235 | |
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236 | #define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)] |
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237 | #define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a] |
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238 | |
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239 | typedef struct { |
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240 | } lpc32xx_nand_slc; |
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241 | |
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242 | typedef struct { |
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243 | } lpc32xx_ssp; |
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244 | |
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245 | typedef struct { |
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246 | } lpc32xx_spi; |
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247 | |
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248 | typedef struct { |
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249 | } lpc32xx_sd_card; |
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250 | |
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251 | typedef struct { |
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252 | } lpc32xx_usb; |
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253 | |
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254 | typedef struct { |
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255 | } lpc32xx_lcd; |
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256 | |
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257 | typedef struct { |
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258 | } lpc32xx_etb; |
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259 | |
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260 | typedef struct { |
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261 | } lpc32xx_syscon; |
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262 | |
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263 | typedef struct { |
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264 | } lpc32xx_uart_ctrl; |
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265 | |
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266 | typedef struct { |
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267 | } lpc32xx_uart; |
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268 | |
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269 | typedef struct { |
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270 | } lpc32xx_ms_timer; |
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271 | |
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272 | typedef struct { |
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273 | } lpc32xx_hs_timer; |
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274 | |
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275 | /** |
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276 | * @name Watchdog Timer Interrupt Status Register (WDTIM_INT) |
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277 | * |
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278 | * @{ |
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279 | */ |
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280 | |
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281 | #define WDTTIM_INT_MATCH_INT BSP_BIT32(0) |
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282 | |
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283 | /** @} */ |
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284 | |
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285 | /** |
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286 | * @name Watchdog Timer Control Register (WDTIM_CTRL) |
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287 | * |
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288 | * @{ |
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289 | */ |
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290 | |
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291 | #define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0) |
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292 | #define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1) |
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293 | #define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2) |
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294 | |
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295 | /** @} */ |
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296 | |
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297 | /** |
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298 | * @name Watchdog Timer Match Control Register (WDTIM_MCTRL) |
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299 | * |
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300 | * @{ |
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301 | */ |
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302 | |
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303 | #define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0) |
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304 | #define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1) |
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305 | #define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2) |
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306 | #define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3) |
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307 | #define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4) |
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308 | #define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5) |
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309 | #define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6) |
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310 | |
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311 | /** @} */ |
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312 | |
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313 | /** |
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314 | * @name Watchdog Timer External Match Control Register (WDTIM_EMR) |
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315 | * |
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316 | * @{ |
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317 | */ |
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318 | |
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319 | #define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0) |
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320 | #define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5) |
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321 | #define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) |
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322 | |
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323 | /** @} */ |
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324 | |
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325 | /** |
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326 | * @name Watchdog Timer Reset Source Register (WDTIM_RES) |
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327 | * |
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328 | * @{ |
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329 | */ |
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330 | |
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331 | #define WDTTIM_RES_WDT BSP_BIT32(0) |
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332 | |
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333 | /** @} */ |
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334 | |
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335 | typedef struct { |
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336 | uint32_t intr; |
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337 | uint32_t ctrl; |
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338 | uint32_t counter; |
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339 | uint32_t mctrl; |
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340 | uint32_t match0; |
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341 | uint32_t emr; |
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342 | uint32_t pulse; |
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343 | uint32_t res; |
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344 | } lpc32xx_wdt; |
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345 | |
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346 | typedef struct { |
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347 | } lpc32xx_debug; |
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348 | |
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349 | typedef struct { |
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350 | } lpc32xx_adc; |
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351 | |
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352 | typedef struct { |
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353 | } lpc32xx_keyscan; |
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354 | |
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355 | typedef struct { |
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356 | } lpc32xx_pwm; |
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357 | |
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358 | typedef struct { |
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359 | } lpc32xx_mcpwm; |
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360 | |
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361 | typedef struct { |
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362 | uint32_t mac1; |
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363 | uint32_t mac2; |
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364 | uint32_t ipgt; |
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365 | uint32_t ipgr; |
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366 | uint32_t clrt; |
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367 | uint32_t maxf; |
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368 | uint32_t supp; |
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369 | uint32_t test; |
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370 | uint32_t mcfg; |
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371 | uint32_t mcmd; |
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372 | uint32_t madr; |
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373 | uint32_t mwtd; |
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374 | uint32_t mrdd; |
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375 | uint32_t mind; |
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376 | uint32_t reserved_0 [2]; |
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377 | uint32_t sa0; |
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378 | uint32_t sa1; |
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379 | uint32_t sa2; |
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380 | uint32_t reserved_1 [45]; |
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381 | uint32_t command; |
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382 | uint32_t status; |
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383 | uint32_t rxdescriptor; |
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384 | uint32_t rxstatus; |
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385 | uint32_t rxdescriptornum; |
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386 | uint32_t rxproduceindex; |
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387 | uint32_t rxconsumeindex; |
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388 | uint32_t txdescriptor; |
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389 | uint32_t txstatus; |
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390 | uint32_t txdescriptornum; |
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391 | uint32_t txproduceindex; |
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392 | uint32_t txconsumeindex; |
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393 | uint32_t reserved_2 [10]; |
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394 | uint32_t tsv0; |
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395 | uint32_t tsv1; |
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396 | uint32_t rsv; |
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397 | uint32_t reserved_3 [3]; |
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398 | uint32_t flowcontrolcnt; |
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399 | uint32_t flowcontrolsts; |
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400 | uint32_t reserved_4 [34]; |
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401 | uint32_t rxfilterctrl; |
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402 | uint32_t rxfilterwolsts; |
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403 | uint32_t rxfilterwolclr; |
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404 | uint32_t reserved_5 [1]; |
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405 | uint32_t hashfilterl; |
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406 | uint32_t hashfilterh; |
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407 | uint32_t reserved_6 [882]; |
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408 | uint32_t intstatus; |
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409 | uint32_t intenable; |
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410 | uint32_t intclear; |
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411 | uint32_t intset; |
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412 | uint32_t reserved_7 [1]; |
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413 | uint32_t powerdown; |
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414 | } lpc32xx_eth; |
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415 | |
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416 | typedef struct { |
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417 | uint32_t er; |
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418 | uint32_t rsr; |
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419 | uint32_t sr; |
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420 | uint32_t apr; |
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421 | uint32_t atr; |
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422 | uint32_t itr; |
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423 | } lpc32xx_irq; |
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424 | |
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425 | typedef struct { |
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426 | uint32_t p3_inp_state; |
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427 | uint32_t p3_outp_set; |
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428 | uint32_t p3_outp_clr; |
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429 | uint32_t p3_outp_state; |
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430 | uint32_t p2_dir_set; |
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431 | uint32_t p2_dir_clr; |
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432 | uint32_t p2_dir_state; |
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433 | uint32_t p2_inp_state; |
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434 | uint32_t p2_outp_set; |
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435 | uint32_t p2_outp_clr; |
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436 | uint32_t p2_mux_set; |
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437 | uint32_t p2_mux_clr; |
---|
438 | uint32_t p2_mux_state; |
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439 | LPC32XX_RESERVE(0x034, 0x040); |
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440 | uint32_t p0_inp_state; |
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441 | uint32_t p0_outp_set; |
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442 | uint32_t p0_outp_clr; |
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443 | uint32_t p0_outp_state; |
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444 | uint32_t p0_dir_set; |
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445 | uint32_t p0_dir_clr; |
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446 | uint32_t p0_dir_state; |
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447 | LPC32XX_RESERVE(0x05c, 0x060); |
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448 | uint32_t p1_inp_state; |
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449 | uint32_t p1_outp_set; |
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450 | uint32_t p1_outp_clr; |
---|
451 | uint32_t p1_outp_state; |
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452 | uint32_t p1_dir_set; |
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453 | uint32_t p1_dir_clr; |
---|
454 | uint32_t p1_dir_state; |
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455 | LPC32XX_RESERVE(0x07c, 0x110); |
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456 | uint32_t p3_mux_set; |
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457 | uint32_t p3_mux_clr; |
---|
458 | uint32_t p3_mux_state; |
---|
459 | uint32_t p0_mux_set; |
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460 | uint32_t p0_mux_clr; |
---|
461 | uint32_t p0_mux_state; |
---|
462 | uint32_t p1_mux_set; |
---|
463 | uint32_t p1_mux_clr; |
---|
464 | uint32_t p1_mux_state; |
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465 | } lpc32xx_gpio; |
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466 | |
---|
467 | typedef struct { |
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468 | uint32_t rx_or_tx; |
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469 | uint32_t stat; |
---|
470 | uint32_t ctrl; |
---|
471 | uint32_t clk_hi; |
---|
472 | uint32_t clk_lo; |
---|
473 | uint32_t adr; |
---|
474 | uint32_t rxfl; |
---|
475 | uint32_t txfl; |
---|
476 | uint32_t rxb; |
---|
477 | uint32_t txb; |
---|
478 | uint32_t s_tx; |
---|
479 | uint32_t s_txfl; |
---|
480 | } lpc32xx_i2c; |
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481 | |
---|
482 | typedef struct { |
---|
483 | uint32_t ucount; |
---|
484 | uint32_t dcount; |
---|
485 | uint32_t match0; |
---|
486 | uint32_t match1; |
---|
487 | uint32_t ctrl; |
---|
488 | uint32_t intstat; |
---|
489 | uint32_t key; |
---|
490 | uint32_t sram [32]; |
---|
491 | } lpc32xx_rtc; |
---|
492 | |
---|
493 | typedef struct { |
---|
494 | uint32_t control; |
---|
495 | uint32_t status; |
---|
496 | uint32_t timeout; |
---|
497 | uint32_t reserved_0 [5]; |
---|
498 | } lpc32xx_emc_ahb; |
---|
499 | |
---|
500 | typedef struct { |
---|
501 | union { |
---|
502 | uint32_t w32; |
---|
503 | uint16_t w16; |
---|
504 | uint8_t w8; |
---|
505 | } buff; |
---|
506 | uint32_t reserved_0 [8191]; |
---|
507 | union { |
---|
508 | uint32_t w32; |
---|
509 | uint16_t w16; |
---|
510 | uint8_t w8; |
---|
511 | } data; |
---|
512 | uint32_t reserved_1 [8191]; |
---|
513 | uint32_t cmd; |
---|
514 | uint32_t addr; |
---|
515 | uint32_t ecc_enc; |
---|
516 | uint32_t ecc_dec; |
---|
517 | uint32_t ecc_auto_enc; |
---|
518 | uint32_t ecc_auto_dec; |
---|
519 | uint32_t rpr; |
---|
520 | uint32_t wpr; |
---|
521 | uint32_t rubp; |
---|
522 | uint32_t robp; |
---|
523 | uint32_t sw_wp_add_low; |
---|
524 | uint32_t sw_wp_add_hig; |
---|
525 | uint32_t icr; |
---|
526 | uint32_t time; |
---|
527 | uint32_t irq_mr; |
---|
528 | uint32_t irq_sr; |
---|
529 | uint32_t reserved_2; |
---|
530 | uint32_t lock_pr; |
---|
531 | uint32_t isr; |
---|
532 | uint32_t ceh; |
---|
533 | } lpc32xx_nand_mlc; |
---|
534 | |
---|
535 | typedef struct { |
---|
536 | lpc32xx_nand_slc nand_slc; |
---|
537 | LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc); |
---|
538 | lpc32xx_ssp ssp_0; |
---|
539 | LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp); |
---|
540 | lpc32xx_spi spi_1; |
---|
541 | LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi); |
---|
542 | lpc32xx_ssp ssp_1; |
---|
543 | LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp); |
---|
544 | lpc32xx_spi spi_2; |
---|
545 | LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi); |
---|
546 | lpc_i2s i2s_0; |
---|
547 | LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s); |
---|
548 | lpc32xx_sd_card sd_card; |
---|
549 | LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card); |
---|
550 | lpc_i2s i2s_1; |
---|
551 | LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s); |
---|
552 | lpc32xx_nand_mlc nand_mlc; |
---|
553 | LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc); |
---|
554 | lpc_dma dma; |
---|
555 | LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma); |
---|
556 | lpc32xx_usb usb; |
---|
557 | LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb); |
---|
558 | lpc32xx_lcd lcd; |
---|
559 | LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd); |
---|
560 | lpc32xx_eth eth; |
---|
561 | LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth); |
---|
562 | lpc_emc emc; |
---|
563 | LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc); |
---|
564 | lpc32xx_emc_ahb emc_ahb [5]; |
---|
565 | LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]); |
---|
566 | lpc32xx_etb etb; |
---|
567 | LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb); |
---|
568 | lpc32xx_syscon syscon; |
---|
569 | LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon); |
---|
570 | lpc32xx_irq mic; |
---|
571 | LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq); |
---|
572 | lpc32xx_irq sic_1; |
---|
573 | LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq); |
---|
574 | lpc32xx_irq sic_2; |
---|
575 | LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq); |
---|
576 | lpc32xx_uart uart_1; |
---|
577 | LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart); |
---|
578 | lpc32xx_uart uart_2; |
---|
579 | LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart); |
---|
580 | lpc32xx_uart uart_7; |
---|
581 | LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart); |
---|
582 | lpc32xx_rtc rtc; |
---|
583 | LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc); |
---|
584 | lpc32xx_gpio gpio; |
---|
585 | LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio); |
---|
586 | lpc_timer timer_4; |
---|
587 | LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer); |
---|
588 | lpc_timer timer_5; |
---|
589 | LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer); |
---|
590 | lpc32xx_ms_timer ms_timer; |
---|
591 | LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer); |
---|
592 | lpc32xx_hs_timer hs_timer; |
---|
593 | LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer); |
---|
594 | lpc32xx_wdt wdt; |
---|
595 | LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt); |
---|
596 | lpc32xx_debug debug; |
---|
597 | LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug); |
---|
598 | lpc_timer timer_0; |
---|
599 | LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer); |
---|
600 | lpc32xx_adc adc; |
---|
601 | LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc); |
---|
602 | lpc_timer timer_1; |
---|
603 | LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer); |
---|
604 | lpc32xx_keyscan keyscan; |
---|
605 | LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan); |
---|
606 | lpc32xx_uart_ctrl uart_ctrl; |
---|
607 | LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl); |
---|
608 | lpc_timer timer_2; |
---|
609 | LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer); |
---|
610 | lpc32xx_pwm pwm_1_and_pwm_2; |
---|
611 | LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm); |
---|
612 | lpc_timer timer3; |
---|
613 | LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer); |
---|
614 | lpc32xx_uart uart_3; |
---|
615 | LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart); |
---|
616 | lpc32xx_uart uart_4; |
---|
617 | LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart); |
---|
618 | lpc32xx_uart uart_5; |
---|
619 | LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart); |
---|
620 | lpc32xx_uart uart_6; |
---|
621 | LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart); |
---|
622 | lpc32xx_i2c i2c_1; |
---|
623 | LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c); |
---|
624 | lpc32xx_i2c i2c_2; |
---|
625 | LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c); |
---|
626 | lpc32xx_mcpwm mcpwm; |
---|
627 | } lpc32xx_registers; |
---|
628 | |
---|
629 | extern volatile lpc32xx_registers lpc32xx; |
---|
630 | |
---|
631 | /** @} */ |
---|
632 | |
---|
633 | #endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */ |
---|