source: rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h @ 598a4505

4.115
Last change on this file since 598a4505 was 598a4505, checked in by Sebastian Huber <sebastian.huber@…>, on Dec 3, 2010 at 9:29:08 AM

2010-12-03 Sebastian Huber <sebastian.huber@…>

  • include/lpc32xx.h: Added I2S module.
  • Makefile.am, bsp_specs, preinstall.am, startup/bspstarthooks.c, startup/linkcmds.lpc32xx, startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1, startup/linkcmds.lpc32xx_mzx_stage_2, startup/linkcmds.lpc32xx_phycore: Update due to linker command file changes.
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc32xx_reg
5 *
6 * @brief Register base addresses.
7 */
8
9/*
10 * Copyright (c) 2009, 2010
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http:
20 */
21
22#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
23#define LIBBSP_ARM_LPC32XX_LPC32XX_H
24
25#include <stdint.h>
26
27#include <bsp/utility.h>
28#include <bsp/lpc-timer.h>
29#include <bsp/lpc-dma.h>
30#include <bsp/lpc-i2s.h>
31
32/**
33 * @defgroup lpc32xx_reg Register Definitions
34 *
35 * @ingroup lpc32xx
36 *
37 * @brief Register definitions.
38 *
39 * @{
40 */
41
42/**
43 * @name Register Base Addresses
44 *
45 * @{
46 */
47
48#define LPC32XX_BASE_ADC 0x40048000
49#define LPC32XX_BASE_SYSCON 0x40004000
50#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
51#define LPC32XX_BASE_DMA 0x31000000
52#define LPC32XX_BASE_EMC 0x31080000
53#define LPC32XX_BASE_EMC_CS_0 0xe0000000
54#define LPC32XX_BASE_EMC_CS_1 0xe1000000
55#define LPC32XX_BASE_EMC_CS_2 0xe2000000
56#define LPC32XX_BASE_EMC_CS_3 0xe3000000
57#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
58#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
59#define LPC32XX_BASE_ETB_CFG 0x310c0000
60#define LPC32XX_BASE_ETB_DATA 0x310e0000
61#define LPC32XX_BASE_ETHERNET 0x31060000
62#define LPC32XX_BASE_GPIO 0x40028000
63#define LPC32XX_BASE_I2C_1 0x400a0000
64#define LPC32XX_BASE_I2C_2 0x400a8000
65#define LPC32XX_BASE_I2S_0 0x20094000
66#define LPC32XX_BASE_I2S_1 0x2009c000
67#define LPC32XX_BASE_IRAM 0x08000000
68#define LPC32XX_BASE_IROM 0x0c000000
69#define LPC32XX_BASE_KEYSCAN 0x40050000
70#define LPC32XX_BASE_LCD 0x31040000
71#define LPC32XX_BASE_MCPWM 0x400e8000
72#define LPC32XX_BASE_MIC 0x40008000
73#define LPC32XX_BASE_NAND_MLC 0x200a8000
74#define LPC32XX_BASE_NAND_SLC 0x20020000
75#define LPC32XX_BASE_PWM_1 0x4005c000
76#define LPC32XX_BASE_PWM_2 0x4005c004
77#define LPC32XX_BASE_PWM_3 0x4002c000
78#define LPC32XX_BASE_PWM_4 0x40030000
79#define LPC32XX_BASE_RTC 0x40024000
80#define LPC32XX_BASE_RTC_RAM 0x40024080
81#define LPC32XX_BASE_SDCARD 0x20098000
82#define LPC32XX_BASE_SIC_1 0x4000c000
83#define LPC32XX_BASE_SIC_2 0x40010000
84#define LPC32XX_BASE_SPI_1 0x20088000
85#define LPC32XX_BASE_SPI_2 0x20090000
86#define LPC32XX_BASE_SSP_0 0x20084000
87#define LPC32XX_BASE_SSP_1 0x2008c000
88#define LPC32XX_BASE_TIMER_0 0x40044000
89#define LPC32XX_BASE_TIMER_1 0x4004c000
90#define LPC32XX_BASE_TIMER_2 0x40058000
91#define LPC32XX_BASE_TIMER_3 0x40060000
92#define LPC32XX_BASE_TIMER_5 0x4002c000
93#define LPC32XX_BASE_TIMER_6 0x40030000
94#define LPC32XX_BASE_TIMER_HS 0x40038000
95#define LPC32XX_BASE_TIMER_MS 0x40034000
96#define LPC32XX_BASE_UART_1 0x40014000
97#define LPC32XX_BASE_UART_2 0x40018000
98#define LPC32XX_BASE_UART_3 0x40080000
99#define LPC32XX_BASE_UART_4 0x40088000
100#define LPC32XX_BASE_UART_5 0x40090000
101#define LPC32XX_BASE_UART_6 0x40098000
102#define LPC32XX_BASE_UART_7 0x4001c000
103#define LPC32XX_BASE_USB 0x31020000
104#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
105#define LPC32XX_BASE_WDT 0x4003c000
106
107/** @} */
108
109/**
110 * @name Miscanellanous Registers
111 *
112 * @{
113 */
114
115#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
116#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
117#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
118#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
119#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
120#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
121#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
122#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
123#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
124#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
125#define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c)
126#define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4)
127#define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8)
128#define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110)
129#define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300)
130#define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300)
131#define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304)
132#define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308)
133#define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c)
134#define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310)
135#define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044)
136#define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c)
137#define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050)
138#define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048)
139#define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058)
140#define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040)
141#define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4)
142#define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec)
143#define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030)
144#define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020)
145#define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018)
146#define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038)
147#define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028)
148#define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034)
149#define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024)
150#define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c)
151#define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c)
152#define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064)
153#define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c)
154#define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080)
155#define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8)
156#define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8)
157#define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090)
158#define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054)
159#define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c)
160#define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078)
161#define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4)
162#define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac)
163#define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0)
164#define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc)
165#define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4)
166#define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060)
167#define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0)
168#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
169#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
170#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
171#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
172#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
173
174/** @} */
175
176/**
177 * @name Power Control Register (PWR_CTRL)
178 *
179 * @{
180 */
181
182#define PWR_STOP BSP_BIT32(0)
183#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
184#define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
185#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
186#define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
187#define PWR_HIGHCORE_HIGH BSP_BIT32(5)
188#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
189#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
190#define PWR_EMCSREFREQ BSP_BIT32(9)
191#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
192
193/** @} */
194
195/**
196 * @name HCLK PLL Control Register (HCLKPLL_CTRL)
197 *
198 * @{
199 */
200
201#define HCLK_PLL_LOCK BSP_BIT32(0)
202#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
203#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
204#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
205#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
206#define HCLK_PLL_DIRECT BSP_BIT32(14)
207#define HCLK_PLL_BYPASS BSP_BIT32(15)
208#define HCLK_PLL_POWER BSP_BIT32(16)
209
210/** @} */
211
212/**
213 * @name HCLK Divider Control Register (HCLKDIV_CTRL)
214 *
215 * @{
216 */
217
218#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
219#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
220#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
221
222/** @} */
223
224#define LPC32XX_RESERVED(a, b, s) (((b) - (a) - sizeof(s)) / 4)
225
226typedef struct {
227} lpc32xx_nand_slc;
228
229typedef struct {
230} lpc32xx_ssp;
231
232typedef struct {
233} lpc32xx_spi;
234
235typedef struct {
236} lpc32xx_sd_card;
237
238typedef struct {
239} lpc32xx_usb;
240
241typedef struct {
242} lpc32xx_lcd;
243
244typedef struct {
245} lpc32xx_etb;
246
247typedef struct {
248} lpc32xx_syscon;
249
250typedef struct {
251} lpc32xx_uart_ctrl;
252
253typedef struct {
254} lpc32xx_uart;
255
256typedef struct {
257} lpc32xx_ms_timer;
258
259typedef struct {
260} lpc32xx_hs_timer;
261
262typedef struct {
263} lpc32xx_wdg_timer;
264
265typedef struct {
266} lpc32xx_debug;
267
268typedef struct {
269} lpc32xx_adc;
270
271typedef struct {
272} lpc32xx_keyscan;
273
274typedef struct {
275} lpc32xx_pwm;
276
277typedef struct {
278} lpc32xx_mcpwm;
279
280typedef struct {
281  uint32_t mac1;
282  uint32_t mac2;
283  uint32_t ipgt;
284  uint32_t ipgr;
285  uint32_t clrt;
286  uint32_t maxf;
287  uint32_t supp;
288  uint32_t test;
289  uint32_t mcfg;
290  uint32_t mcmd;
291  uint32_t madr;
292  uint32_t mwtd;
293  uint32_t mrdd;
294  uint32_t mind;
295  uint32_t reserved_0 [2];
296  uint32_t sa0;
297  uint32_t sa1;
298  uint32_t sa2;
299  uint32_t reserved_1 [45];
300  uint32_t command;
301  uint32_t status;
302  uint32_t rxdescriptor;
303  uint32_t rxstatus;
304  uint32_t rxdescriptornum;
305  uint32_t rxproduceindex;
306  uint32_t rxconsumeindex;
307  uint32_t txdescriptor;
308  uint32_t txstatus;
309  uint32_t txdescriptornum;
310  uint32_t txproduceindex;
311  uint32_t txconsumeindex;
312  uint32_t reserved_2 [10];
313  uint32_t tsv0;
314  uint32_t tsv1;
315  uint32_t rsv;
316  uint32_t reserved_3 [3];
317  uint32_t flowcontrolcnt;
318  uint32_t flowcontrolsts;
319  uint32_t reserved_4 [34];
320  uint32_t rxfilterctrl;
321  uint32_t rxfilterwolsts;
322  uint32_t rxfilterwolclr;
323  uint32_t reserved_5 [1];
324  uint32_t hashfilterl;
325  uint32_t hashfilterh;
326  uint32_t reserved_6 [882];
327  uint32_t intstatus;
328  uint32_t intenable;
329  uint32_t intclear;
330  uint32_t intset;
331  uint32_t reserved_7 [1];
332  uint32_t powerdown;
333} lpc32xx_eth;
334
335typedef struct {
336  uint32_t er;
337  uint32_t rsr;
338  uint32_t sr;
339  uint32_t apr;
340  uint32_t atr;
341  uint32_t itr;
342} lpc32xx_irq;
343
344typedef struct {
345  uint32_t p3_inp_state;
346  uint32_t p3_outp_set;
347  uint32_t p3_outp_clr;
348  uint32_t p3_outp_state;
349  uint32_t p2_dir_set;
350  uint32_t p2_dir_clr;
351  uint32_t p2_dir_state;
352  uint32_t p2_inp_state;
353  uint32_t p2_outp_set;
354  uint32_t p2_outp_clr;
355  uint32_t reserved_0 [6];
356  uint32_t p0_inp_state;
357  uint32_t p0_outp_set;
358  uint32_t p0_outp_clr;
359  uint32_t p0_outp_state;
360  uint32_t p0_dir_set;
361  uint32_t p0_dir_clr;
362  uint32_t p0_dir_state;
363  uint32_t reserved_1 [1];
364  uint32_t p1_inp_state;
365  uint32_t p1_outp_set;
366  uint32_t p1_outp_clr;
367  uint32_t p1_outp_state;
368  uint32_t p1_dir_set;
369  uint32_t p1_dir_clr;
370  uint32_t p1_dir_state;
371} lpc32xx_gpio;
372
373typedef struct {
374  uint32_t rx_or_tx;
375  uint32_t stat;
376  uint32_t ctrl;
377  uint32_t clk_hi;
378  uint32_t clk_lo;
379  uint32_t adr;
380  uint32_t rxfl;
381  uint32_t txfl;
382  uint32_t rxb;
383  uint32_t txb;
384  uint32_t s_tx;
385  uint32_t s_txfl;
386} lpc32xx_i2c;
387
388typedef struct {
389  uint32_t ucount;
390  uint32_t dcount;
391  uint32_t match0;
392  uint32_t match1;
393  uint32_t ctrl;
394  uint32_t intstat;
395  uint32_t key;
396  uint32_t sram [32];
397} lpc32xx_rtc;
398
399#define EMC_DYN_CHIP_COUNT 2
400
401#define EMC_STATIC_CHIP_COUNT 4
402
403typedef struct {
404  uint32_t config;
405  uint32_t rascas;
406  uint32_t reserved_0 [6];
407} lpc32xx_emc_dynamic;
408
409typedef struct {
410  uint32_t config;
411  uint32_t waitwen;
412  uint32_t waitoen;
413  uint32_t waitrd;
414  uint32_t waitpage;
415  uint32_t waitwr;
416  uint32_t waitturn;
417  uint32_t reserved_0 [1];
418} lpc32xx_emc_static;
419
420typedef struct {
421  uint32_t control;
422  uint32_t status;
423  uint32_t timeout;
424  uint32_t reserved_0 [5];
425} lpc32xx_emc_ahb;
426
427typedef struct {
428  uint32_t control;
429  uint32_t status;
430  uint32_t config;
431  uint32_t reserved_0 [5];
432  uint32_t dynamiccontrol;
433  uint32_t dynamicrefresh;
434  uint32_t dynamicreadconfig;
435  uint32_t reserved_1;
436  uint32_t dynamictrp;
437  uint32_t dynamictras;
438  uint32_t dynamictsrex;
439  uint32_t reserved_2 [2];
440  uint32_t dynamictwr;
441  uint32_t dynamictrc;
442  uint32_t dynamictrfc;
443  uint32_t dynamictxsr;
444  uint32_t dynamictrrd;
445  uint32_t dynamictmrd;
446  uint32_t dynamictcdlr;
447  uint32_t reserved_3 [8];
448  uint32_t staticextendedwait;
449  uint32_t reserved_4 [31];
450  lpc32xx_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
451  uint32_t reserved_5 [48];
452  lpc32xx_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
453  uint32_t reserved_6 [96];
454  lpc32xx_emc_ahb ahb [5];
455} lpc32xx_emc;
456
457typedef struct {
458  union {
459    uint32_t w32;
460    uint16_t w16;
461    uint8_t w8;
462  } buff;
463  uint32_t reserved_0 [8191];
464  union {
465    uint32_t w32;
466    uint16_t w16;
467    uint8_t w8;
468  } data;
469  uint32_t reserved_1 [8191];
470  uint32_t cmd;
471  uint32_t addr;
472  uint32_t ecc_enc;
473  uint32_t ecc_dec;
474  uint32_t ecc_auto_enc;
475  uint32_t ecc_auto_dec;
476  uint32_t rpr;
477  uint32_t wpr;
478  uint32_t rubp;
479  uint32_t robp;
480  uint32_t sw_wp_add_low;
481  uint32_t sw_wp_add_hig;
482  uint32_t icr;
483  uint32_t time;
484  uint32_t irq_mr;
485  uint32_t irq_sr;
486  uint32_t lock_pr;
487  uint32_t isr;
488  uint32_t ceh;
489} lpc32xx_nand_mlc;
490
491typedef struct {
492  lpc32xx_nand_slc nand_slc;
493  uint32_t reserved_0 [LPC32XX_RESERVED(0x20020000, 0x20084000, lpc32xx_nand_slc)];
494  lpc32xx_ssp ssp_0;
495  uint32_t reserved_1 [LPC32XX_RESERVED(0x20084000, 0x20088000, lpc32xx_ssp)]; 
496  lpc32xx_spi spi_1;
497  uint32_t reserved_2 [LPC32XX_RESERVED(0x20088000, 0x2008c000, lpc32xx_spi)];
498  lpc32xx_ssp ssp_1;
499  uint32_t reserved_3 [LPC32XX_RESERVED(0x2008c000, 0x20090000, lpc32xx_ssp)];
500  lpc32xx_spi spi_2;
501  uint32_t reserved_4 [LPC32XX_RESERVED(0x20090000, 0x20094000, lpc32xx_spi)];
502  lpc_i2s i2s_0;
503  uint32_t reserved_5 [LPC32XX_RESERVED(0x20094000, 0x20098000, lpc_i2s)];
504  lpc32xx_sd_card sd_card;
505  uint32_t reserved_6 [LPC32XX_RESERVED(0x20098000, 0x2009c000, lpc32xx_sd_card)];
506  lpc_i2s i2s_1;
507  uint32_t reserved_7 [LPC32XX_RESERVED(0x2009c000, 0x200a8000, lpc_i2s)];
508  lpc32xx_nand_mlc nand_mlc;
509  uint32_t reserved_8 [LPC32XX_RESERVED(0x200a8000, 0x31000000, lpc32xx_nand_mlc)];
510  lpc_dma dma;
511  uint32_t reserved_9 [LPC32XX_RESERVED(0x31000000, 0x31020000, lpc_dma)];
512  lpc32xx_usb usb;
513  uint32_t reserved_10 [LPC32XX_RESERVED(0x31020000, 0x31040000, lpc32xx_usb)];
514  lpc32xx_lcd lcd;
515  uint32_t reserved_11 [LPC32XX_RESERVED(0x31040000, 0x31060000, lpc32xx_lcd)];
516  lpc32xx_eth eth;
517  uint32_t reserved_12 [LPC32XX_RESERVED(0x31060000, 0x31080000, lpc32xx_eth)];
518  lpc32xx_emc emc;
519  uint32_t reserved_13 [LPC32XX_RESERVED(0x31080000, 0x310c0000, lpc32xx_emc)];
520  lpc32xx_etb etb;
521  uint32_t reserved_14 [LPC32XX_RESERVED(0x310c0000, 0x40004000, lpc32xx_etb)];
522  lpc32xx_syscon syscon;
523  uint32_t reserved_15 [LPC32XX_RESERVED(0x40004000, 0x40008000, lpc32xx_syscon)];
524  lpc32xx_irq mic;
525  uint32_t reserved_16 [LPC32XX_RESERVED(0x40008000, 0x4000c000, lpc32xx_irq)];
526  lpc32xx_irq sic_1;
527  uint32_t reserved_17 [LPC32XX_RESERVED(0x4000c000, 0x40010000, lpc32xx_irq)];
528  lpc32xx_irq sic_2;
529  uint32_t reserved_18 [LPC32XX_RESERVED(0x40010000, 0x40014000, lpc32xx_irq)];
530  lpc32xx_uart uart_1;
531  uint32_t reserved_19 [LPC32XX_RESERVED(0x40014000, 0x40018000, lpc32xx_uart)];
532  lpc32xx_uart uart_2;
533  uint32_t reserved_20 [LPC32XX_RESERVED(0x40018000, 0x4001c000, lpc32xx_uart)];
534  lpc32xx_uart uart_7;
535  uint32_t reserved_21 [LPC32XX_RESERVED(0x4001c000, 0x40024000, lpc32xx_uart)];
536  lpc32xx_rtc rtc;
537  uint32_t reserved_22 [LPC32XX_RESERVED(0x40024000, 0x40028000, lpc32xx_rtc)];
538  lpc32xx_gpio gpio;
539  uint32_t reserved_23 [LPC32XX_RESERVED(0x40028000, 0x4002c000, lpc32xx_gpio)];
540  lpc_timer timer_4;
541  uint32_t reserved_24 [LPC32XX_RESERVED(0x4002c000, 0x40030000, lpc_timer)];
542  lpc_timer timer_5;
543  uint32_t reserved_25 [LPC32XX_RESERVED(0x40030000, 0x40034000, lpc_timer)];
544  lpc32xx_ms_timer ms_timer;
545  uint32_t reserved_26 [LPC32XX_RESERVED(0x40034000, 0x40038000, lpc32xx_ms_timer)];
546  lpc32xx_hs_timer hs_timer;
547  uint32_t reserved_27 [LPC32XX_RESERVED(0x40038000, 0x4003c000, lpc32xx_hs_timer)];
548  lpc32xx_wdg_timer wdg_timer;
549  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdg_timer)];
550  lpc32xx_debug debug;
551  uint32_t reserved_29 [LPC32XX_RESERVED(0x40040000, 0x40044000, lpc32xx_debug)];
552  lpc_timer timer_0;
553  uint32_t reserved_30 [LPC32XX_RESERVED(0x40044000, 0x40048000, lpc_timer)];
554  lpc32xx_adc adc;
555  uint32_t reserved_31 [LPC32XX_RESERVED(0x40048000, 0x4004c000, lpc32xx_adc)];
556  lpc_timer timer_1;
557  uint32_t reserved_32 [LPC32XX_RESERVED(0x4004c000, 0x40050000, lpc_timer)];
558  lpc32xx_keyscan keyscan;
559  uint32_t reserved_33 [LPC32XX_RESERVED(0x40050000, 0x40054000, lpc32xx_keyscan)];
560  lpc32xx_uart_ctrl uart_ctrl;
561  uint32_t reserved_34 [LPC32XX_RESERVED(0x40054000, 0x40058000, lpc32xx_uart_ctrl)];
562  lpc_timer timer_2;
563  uint32_t reserved_35 [LPC32XX_RESERVED(0x40058000, 0x4005c000, lpc_timer)];
564  lpc32xx_pwm pwm_1_and_pwm_2;
565  uint32_t reserved_36 [LPC32XX_RESERVED(0x4005c000, 0x40060000, lpc32xx_pwm)];
566  lpc_timer timer3;
567  uint32_t reserved_37 [LPC32XX_RESERVED(0x40060000, 0x40080000, lpc_timer)];
568  lpc32xx_uart uart_3;
569  uint32_t reserved_38 [LPC32XX_RESERVED(0x40080000, 0x40088000, lpc32xx_uart)];
570  lpc32xx_uart uart_4;
571  uint32_t reserved_39 [LPC32XX_RESERVED(0x40088000, 0x40090000, lpc32xx_uart)];
572  lpc32xx_uart uart_5;
573  uint32_t reserved_40 [LPC32XX_RESERVED(0x40090000, 0x40098000, lpc32xx_uart)];
574  lpc32xx_uart uart_6;
575  uint32_t reserved_41 [LPC32XX_RESERVED(0x40098000, 0x400a0000, lpc32xx_uart)];
576  lpc32xx_i2c i2c_1;
577  uint32_t reserved_42 [LPC32XX_RESERVED(0x400a0000, 0x400a8000, lpc32xx_i2c)];
578  lpc32xx_i2c i2c_2;
579  uint32_t reserved_43 [LPC32XX_RESERVED(0x400a8000, 0x400e8000, lpc32xx_i2c)];
580  lpc32xx_mcpwm mcpwm;
581} lpc32xx_registers;
582
583extern volatile lpc32xx_registers lpc32xx;
584
585/** @} */
586
587#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
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