source: rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h @ 39c8fdb

4.104.115
Last change on this file since 39c8fdb was 39c8fdb, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 01/12/10 at 15:03:22

add support for lpc32xx
  • Property mode set to 100644
File size: 3.3 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc32xx
5 *
6 * @brief Register base addresses.
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http:
20 */
21
22#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
23#define LIBBSP_ARM_LPC32XX_LPC32XX_H
24
25#define LPC32XX_BASE_ADC 0x40048000
26#define LPC32XX_BASE_SYSCON 0x40004000
27#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
28#define LPC32XX_BASE_DMA 0x31000000
29#define LPC32XX_BASE_EMC 0x31080000
30#define LPC32XX_BASE_EMC_CS_0 0xe0000000
31#define LPC32XX_BASE_EMC_CS_1 0xe1000000
32#define LPC32XX_BASE_EMC_CS_2 0xe2000000
33#define LPC32XX_BASE_EMC_CS_3 0xe3000000
34#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
35#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
36#define LPC32XX_BASE_ETB_CFG 0x310c0000
37#define LPC32XX_BASE_ETB_DATA 0x310e0000
38#define LPC32XX_BASE_ETHERNET 0x31060000
39#define LPC32XX_BASE_GPIO 0x40028000
40#define LPC32XX_BASE_I2C_1 0x400a0000
41#define LPC32XX_BASE_I2C_2 0x400a8000
42#define LPC32XX_BASE_I2S_0 0x20094000
43#define LPC32XX_BASE_I2S_1 0x2009c000
44#define LPC32XX_BASE_IRAM 0x08000000
45#define LPC32XX_BASE_IROM 0x0c000000
46#define LPC32XX_BASE_KEYSCAN 0x40050000
47#define LPC32XX_BASE_LCD 0x31040000
48#define LPC32XX_BASE_MCPWM 0x400e8000
49#define LPC32XX_BASE_MIC 0x40008000
50#define LPC32XX_BASE_NAND_MLC 0x200a8000
51#define LPC32XX_BASE_NAND_SLC 0x20020000
52#define LPC32XX_BASE_PWM_1 0x4005c000
53#define LPC32XX_BASE_PWM_2 0x4005c004
54#define LPC32XX_BASE_PWM_3 0x4002c000
55#define LPC32XX_BASE_PWM_4 0x40030000
56#define LPC32XX_BASE_RTC 0x40024000
57#define LPC32XX_BASE_RTC_RAM 0x40024080
58#define LPC32XX_BASE_SDCARD 0x20098000
59#define LPC32XX_BASE_SIC_1 0x4000c000
60#define LPC32XX_BASE_SIC_2 0x40010000
61#define LPC32XX_BASE_SPI_1 0x20088000
62#define LPC32XX_BASE_SPI_2 0x20090000
63#define LPC32XX_BASE_SSP_0 0x20084000
64#define LPC32XX_BASE_SSP_1 0x2008c000
65#define LPC32XX_BASE_TIMER_0 0x40044000
66#define LPC32XX_BASE_TIMER_1 0x4004c000
67#define LPC32XX_BASE_TIMER_2 0x40058000
68#define LPC32XX_BASE_TIMER_3 0x40060000
69#define LPC32XX_BASE_TIMER_5 0x4002c000
70#define LPC32XX_BASE_TIMER_6 0x40030000
71#define LPC32XX_BASE_TIMER_HS 0x40038000
72#define LPC32XX_BASE_TIMER_MS 0x40034000
73#define LPC32XX_BASE_UART_1 0x40014000
74#define LPC32XX_BASE_UART_2 0x40018000
75#define LPC32XX_BASE_UART_3 0x40080000
76#define LPC32XX_BASE_UART_4 0x40088000
77#define LPC32XX_BASE_UART_5 0x40090000
78#define LPC32XX_BASE_UART_6 0x40098000
79#define LPC32XX_BASE_UART_7 0x4001c000
80#define LPC32XX_BASE_USB 0x31020000
81#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
82#define LPC32XX_BASE_WDT 0x4003c000
83
84#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
85#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
86#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
87#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
88#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
89#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
90#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
91#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
92#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
93#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
94
95#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
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