source: rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h @ 2d6543d4

4.115
Last change on this file since 2d6543d4 was 2d6543d4, checked in by Daniel Ramirez <javamonn@…>, on 11/30/13 at 02:18:44

doxygen: refactored doxygen in libbsp/arm/lpc32xx

This patch refactors a lot of the existing doxygen within libbsp/arm/lpc32xx.
Much of this refactoring was just renaming of existing groups to conform to a
more consistent naming structure. With the addition of a doxygen header for
tm27.h, all files within lpc32xx belong to doxygen group now. lpc32xx should
be used a reference for adding doxygen to other bsps.
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc32xx_reg
5 *
6 * @brief Register base addresses.
7 */
8
9/*
10 * Copyright (c) 2009, 2010
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http:
20 */
21
22#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
23#define LIBBSP_ARM_LPC32XX_LPC32XX_H
24
25#include <stdint.h>
26
27#include <bsp/utility.h>
28#include <bsp/lpc-timer.h>
29#include <bsp/lpc-dma.h>
30#include <bsp/lpc-i2s.h>
31#include <bsp/lpc-emc.h>
32
33/**
34 * @defgroup lpc32xx_reg Register Definitions
35 *
36 * @ingroup arm_lpc32xx
37 *
38 * @brief Register definitions.
39 *
40 * @{
41 */
42
43/**
44 * @name Register Base Addresses
45 *
46 * @{
47 */
48
49#define LPC32XX_BASE_ADC 0x40048000
50#define LPC32XX_BASE_SYSCON 0x40004000
51#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
52#define LPC32XX_BASE_DMA 0x31000000
53#define LPC32XX_BASE_EMC 0x31080000
54#define LPC32XX_BASE_EMC_CS_0 0xe0000000
55#define LPC32XX_BASE_EMC_CS_1 0xe1000000
56#define LPC32XX_BASE_EMC_CS_2 0xe2000000
57#define LPC32XX_BASE_EMC_CS_3 0xe3000000
58#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
59#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
60#define LPC32XX_BASE_ETB_CFG 0x310c0000
61#define LPC32XX_BASE_ETB_DATA 0x310e0000
62#define LPC32XX_BASE_ETHERNET 0x31060000
63#define LPC32XX_BASE_GPIO 0x40028000
64#define LPC32XX_BASE_I2C_1 0x400a0000
65#define LPC32XX_BASE_I2C_2 0x400a8000
66#define LPC32XX_BASE_I2S_0 0x20094000
67#define LPC32XX_BASE_I2S_1 0x2009c000
68#define LPC32XX_BASE_IRAM 0x08000000
69#define LPC32XX_BASE_IROM 0x0c000000
70#define LPC32XX_BASE_KEYSCAN 0x40050000
71#define LPC32XX_BASE_LCD 0x31040000
72#define LPC32XX_BASE_MCPWM 0x400e8000
73#define LPC32XX_BASE_MIC 0x40008000
74#define LPC32XX_BASE_NAND_MLC 0x200a8000
75#define LPC32XX_BASE_NAND_SLC 0x20020000
76#define LPC32XX_BASE_PWM_1 0x4005c000
77#define LPC32XX_BASE_PWM_2 0x4005c004
78#define LPC32XX_BASE_PWM_3 0x4002c000
79#define LPC32XX_BASE_PWM_4 0x40030000
80#define LPC32XX_BASE_RTC 0x40024000
81#define LPC32XX_BASE_RTC_RAM 0x40024080
82#define LPC32XX_BASE_SDCARD 0x20098000
83#define LPC32XX_BASE_SIC_1 0x4000c000
84#define LPC32XX_BASE_SIC_2 0x40010000
85#define LPC32XX_BASE_SPI_1 0x20088000
86#define LPC32XX_BASE_SPI_2 0x20090000
87#define LPC32XX_BASE_SSP_0 0x20084000
88#define LPC32XX_BASE_SSP_1 0x2008c000
89#define LPC32XX_BASE_TIMER_0 0x40044000
90#define LPC32XX_BASE_TIMER_1 0x4004c000
91#define LPC32XX_BASE_TIMER_2 0x40058000
92#define LPC32XX_BASE_TIMER_3 0x40060000
93#define LPC32XX_BASE_TIMER_5 0x4002c000
94#define LPC32XX_BASE_TIMER_6 0x40030000
95#define LPC32XX_BASE_TIMER_HS 0x40038000
96#define LPC32XX_BASE_TIMER_MS 0x40034000
97#define LPC32XX_BASE_UART_1 0x40014000
98#define LPC32XX_BASE_UART_2 0x40018000
99#define LPC32XX_BASE_UART_3 0x40080000
100#define LPC32XX_BASE_UART_4 0x40088000
101#define LPC32XX_BASE_UART_5 0x40090000
102#define LPC32XX_BASE_UART_6 0x40098000
103#define LPC32XX_BASE_UART_7 0x4001c000
104#define LPC32XX_BASE_USB 0x31020000
105#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
106#define LPC32XX_BASE_WDT 0x4003c000
107
108/** @} */
109
110/**
111 * @name Miscanellanous Registers
112 *
113 * @{
114 */
115
116#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
117#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
118#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
119#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
120#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
121#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
122#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
123#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
124#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
125#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
126#define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c)
127#define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4)
128#define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8)
129#define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110)
130#define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300)
131#define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300)
132#define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304)
133#define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308)
134#define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c)
135#define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310)
136#define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044)
137#define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c)
138#define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050)
139#define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048)
140#define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058)
141#define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040)
142#define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4)
143#define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec)
144#define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030)
145#define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020)
146#define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018)
147#define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038)
148#define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028)
149#define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034)
150#define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024)
151#define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c)
152#define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c)
153#define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064)
154#define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c)
155#define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080)
156#define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8)
157#define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8)
158#define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090)
159#define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054)
160#define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c)
161#define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078)
162#define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4)
163#define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac)
164#define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0)
165#define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc)
166#define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4)
167#define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060)
168#define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0)
169#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
170#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
171#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
172#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
173#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
174
175/** @} */
176
177/**
178 * @name Power Control Register (PWR_CTRL)
179 *
180 * @{
181 */
182
183#define PWR_STOP BSP_BIT32(0)
184#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
185#define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
186#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
187#define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
188#define PWR_HIGHCORE_HIGH BSP_BIT32(5)
189#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
190#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
191#define PWR_EMCSREFREQ BSP_BIT32(9)
192#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
193
194/** @} */
195
196/**
197 * @name HCLK PLL Control Register (HCLKPLL_CTRL)
198 *
199 * @{
200 */
201
202#define HCLK_PLL_LOCK BSP_BIT32(0)
203#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
204#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)
205#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
206#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)
207#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
208#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)
209#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
210#define HCLK_PLL_DIRECT BSP_BIT32(14)
211#define HCLK_PLL_BYPASS BSP_BIT32(15)
212#define HCLK_PLL_POWER BSP_BIT32(16)
213
214/** @} */
215
216/**
217 * @name HCLK Divider Control Register (HCLKDIV_CTRL)
218 *
219 * @{
220 */
221
222#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
223#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)
224#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
225#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)
226#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
227#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)
228
229/** @} */
230
231/**
232 * @name Timer Clock Control Register (TIMCLK_CTRL)
233 *
234 * @{
235 */
236
237#define TIMCLK_CTRL_WDT BSP_BIT32(0)
238#define TIMCLK_CTRL_HST BSP_BIT32(1)
239
240/** @} */
241
242#define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
243#define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
244
245typedef struct {
246} lpc32xx_nand_slc;
247
248typedef struct {
249} lpc32xx_ssp;
250
251typedef struct {
252} lpc32xx_spi;
253
254typedef struct {
255} lpc32xx_sd_card;
256
257typedef struct {
258} lpc32xx_usb;
259
260typedef struct {
261} lpc32xx_lcd;
262
263typedef struct {
264} lpc32xx_etb;
265
266typedef struct {
267} lpc32xx_syscon;
268
269typedef struct {
270} lpc32xx_uart_ctrl;
271
272typedef struct {
273} lpc32xx_uart;
274
275typedef struct {
276} lpc32xx_ms_timer;
277
278typedef struct {
279} lpc32xx_hs_timer;
280
281/**
282 * @name Watchdog Timer Interrupt Status Register (WDTIM_INT)
283 *
284 * @{
285 */
286
287#define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
288
289/** @} */
290
291/**
292 * @name Watchdog Timer Control Register (WDTIM_CTRL)
293 *
294 * @{
295 */
296
297#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
298#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
299#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
300
301/** @} */
302
303/**
304 * @name Watchdog Timer Match Control Register (WDTIM_MCTRL)
305 *
306 * @{
307 */
308
309#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
310#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
311#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
312#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
313#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
314#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
315#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
316
317/** @} */
318
319/**
320 * @name Watchdog Timer External Match Control Register (WDTIM_EMR)
321 *
322 * @{
323 */
324
325#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
326#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
327#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
328
329/** @} */
330
331/**
332 * @name Watchdog Timer Reset Source Register (WDTIM_RES)
333 *
334 * @{
335 */
336
337#define WDTTIM_RES_WDT BSP_BIT32(0)
338
339/** @} */
340
341typedef struct {
342  uint32_t intr;
343  uint32_t ctrl;
344  uint32_t counter;
345  uint32_t mctrl;
346  uint32_t match0;
347  uint32_t emr;
348  uint32_t pulse;
349  uint32_t res;
350} lpc32xx_wdt;
351
352typedef struct {
353} lpc32xx_debug;
354
355typedef struct {
356} lpc32xx_adc;
357
358typedef struct {
359} lpc32xx_keyscan;
360
361typedef struct {
362} lpc32xx_pwm;
363
364typedef struct {
365} lpc32xx_mcpwm;
366
367typedef struct {
368  uint32_t mac1;
369  uint32_t mac2;
370  uint32_t ipgt;
371  uint32_t ipgr;
372  uint32_t clrt;
373  uint32_t maxf;
374  uint32_t supp;
375  uint32_t test;
376  uint32_t mcfg;
377  uint32_t mcmd;
378  uint32_t madr;
379  uint32_t mwtd;
380  uint32_t mrdd;
381  uint32_t mind;
382  uint32_t reserved_0 [2];
383  uint32_t sa0;
384  uint32_t sa1;
385  uint32_t sa2;
386  uint32_t reserved_1 [45];
387  uint32_t command;
388  uint32_t status;
389  uint32_t rxdescriptor;
390  uint32_t rxstatus;
391  uint32_t rxdescriptornum;
392  uint32_t rxproduceindex;
393  uint32_t rxconsumeindex;
394  uint32_t txdescriptor;
395  uint32_t txstatus;
396  uint32_t txdescriptornum;
397  uint32_t txproduceindex;
398  uint32_t txconsumeindex;
399  uint32_t reserved_2 [10];
400  uint32_t tsv0;
401  uint32_t tsv1;
402  uint32_t rsv;
403  uint32_t reserved_3 [3];
404  uint32_t flowcontrolcnt;
405  uint32_t flowcontrolsts;
406  uint32_t reserved_4 [34];
407  uint32_t rxfilterctrl;
408  uint32_t rxfilterwolsts;
409  uint32_t rxfilterwolclr;
410  uint32_t reserved_5 [1];
411  uint32_t hashfilterl;
412  uint32_t hashfilterh;
413  uint32_t reserved_6 [882];
414  uint32_t intstatus;
415  uint32_t intenable;
416  uint32_t intclear;
417  uint32_t intset;
418  uint32_t reserved_7 [1];
419  uint32_t powerdown;
420} lpc32xx_eth;
421
422typedef struct {
423  uint32_t er;
424  uint32_t rsr;
425  uint32_t sr;
426  uint32_t apr;
427  uint32_t atr;
428  uint32_t itr;
429} lpc32xx_irq;
430
431typedef struct {
432  uint32_t p3_inp_state;
433  uint32_t p3_outp_set;
434  uint32_t p3_outp_clr;
435  uint32_t p3_outp_state;
436  uint32_t p2_dir_set;
437  uint32_t p2_dir_clr;
438  uint32_t p2_dir_state;
439  uint32_t p2_inp_state;
440  uint32_t p2_outp_set;
441  uint32_t p2_outp_clr;
442  uint32_t p2_mux_set;
443  uint32_t p2_mux_clr;
444  uint32_t p2_mux_state;
445  LPC32XX_RESERVE(0x034, 0x040);
446  uint32_t p0_inp_state;
447  uint32_t p0_outp_set;
448  uint32_t p0_outp_clr;
449  uint32_t p0_outp_state;
450  uint32_t p0_dir_set;
451  uint32_t p0_dir_clr;
452  uint32_t p0_dir_state;
453  LPC32XX_RESERVE(0x05c, 0x060);
454  uint32_t p1_inp_state;
455  uint32_t p1_outp_set;
456  uint32_t p1_outp_clr;
457  uint32_t p1_outp_state;
458  uint32_t p1_dir_set;
459  uint32_t p1_dir_clr;
460  uint32_t p1_dir_state;
461  LPC32XX_RESERVE(0x07c, 0x110);
462  uint32_t p3_mux_set;
463  uint32_t p3_mux_clr;
464  uint32_t p3_mux_state;
465  LPC32XX_RESERVE(0x11c, 0x120);
466  uint32_t p0_mux_set;
467  uint32_t p0_mux_clr;
468  uint32_t p0_mux_state;
469  LPC32XX_RESERVE(0x12c, 0x130);
470  uint32_t p1_mux_set;
471  uint32_t p1_mux_clr;
472  uint32_t p1_mux_state;
473} lpc32xx_gpio;
474
475typedef struct {
476  uint32_t rx_or_tx;
477  uint32_t stat;
478  uint32_t ctrl;
479  uint32_t clk_hi;
480  uint32_t clk_lo;
481  uint32_t adr;
482  uint32_t rxfl;
483  uint32_t txfl;
484  uint32_t rxb;
485  uint32_t txb;
486  uint32_t s_tx;
487  uint32_t s_txfl;
488} lpc32xx_i2c;
489
490typedef struct {
491  uint32_t ucount;
492  uint32_t dcount;
493  uint32_t match0;
494  uint32_t match1;
495  uint32_t ctrl;
496  uint32_t intstat;
497  uint32_t key;
498  uint32_t sram [32];
499} lpc32xx_rtc;
500
501typedef struct {
502  uint32_t control;
503  uint32_t status;
504  uint32_t timeout;
505  uint32_t reserved_0 [5];
506} lpc32xx_emc_ahb;
507
508typedef struct {
509  union {
510    uint32_t w32;
511    uint16_t w16;
512    uint8_t w8;
513  } buff;
514  uint32_t reserved_0 [8191];
515  union {
516    uint32_t w32;
517    uint16_t w16;
518    uint8_t w8;
519  } data;
520  uint32_t reserved_1 [8191];
521  uint32_t cmd;
522  uint32_t addr;
523  uint32_t ecc_enc;
524  uint32_t ecc_dec;
525  uint32_t ecc_auto_enc;
526  uint32_t ecc_auto_dec;
527  uint32_t rpr;
528  uint32_t wpr;
529  uint32_t rubp;
530  uint32_t robp;
531  uint32_t sw_wp_add_low;
532  uint32_t sw_wp_add_hig;
533  uint32_t icr;
534  uint32_t time;
535  uint32_t irq_mr;
536  uint32_t irq_sr;
537  uint32_t reserved_2;
538  uint32_t lock_pr;
539  uint32_t isr;
540  uint32_t ceh;
541} lpc32xx_nand_mlc;
542
543typedef struct {
544  lpc32xx_nand_slc nand_slc;
545  LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc);
546  lpc32xx_ssp ssp_0;
547  LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp);
548  lpc32xx_spi spi_1;
549  LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi);
550  lpc32xx_ssp ssp_1;
551  LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp);
552  lpc32xx_spi spi_2;
553  LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi);
554  lpc_i2s i2s_0;
555  LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s);
556  lpc32xx_sd_card sd_card;
557  LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card);
558  lpc_i2s i2s_1;
559  LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s);
560  lpc32xx_nand_mlc nand_mlc;
561  LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc);
562  lpc_dma dma;
563  LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma);
564  lpc32xx_usb usb;
565  LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb);
566  lpc32xx_lcd lcd;
567  LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd);
568  lpc32xx_eth eth;
569  LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth);
570  lpc_emc emc;
571  LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc);
572  lpc32xx_emc_ahb emc_ahb [5];
573  LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]);
574  lpc32xx_etb etb;
575  LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb);
576  lpc32xx_syscon syscon;
577  LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon);
578  lpc32xx_irq mic;
579  LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq);
580  lpc32xx_irq sic_1;
581  LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq);
582  lpc32xx_irq sic_2;
583  LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq);
584  lpc32xx_uart uart_1;
585  LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart);
586  lpc32xx_uart uart_2;
587  LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart);
588  lpc32xx_uart uart_7;
589  LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart);
590  lpc32xx_rtc rtc;
591  LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc);
592  lpc32xx_gpio gpio;
593  LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio);
594  lpc_timer timer_4;
595  LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer);
596  lpc_timer timer_5;
597  LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer);
598  lpc32xx_ms_timer ms_timer;
599  LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer);
600  lpc32xx_hs_timer hs_timer;
601  LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer);
602  lpc32xx_wdt wdt;
603  LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt);
604  lpc32xx_debug debug;
605  LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug);
606  lpc_timer timer_0;
607  LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer);
608  lpc32xx_adc adc;
609  LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc);
610  lpc_timer timer_1;
611  LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer);
612  lpc32xx_keyscan keyscan;
613  LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan);
614  lpc32xx_uart_ctrl uart_ctrl;
615  LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl);
616  lpc_timer timer_2;
617  LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer);
618  lpc32xx_pwm pwm_1_and_pwm_2;
619  LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm);
620  lpc_timer timer3;
621  LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer);
622  lpc32xx_uart uart_3;
623  LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart);
624  lpc32xx_uart uart_4;
625  LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart);
626  lpc32xx_uart uart_5;
627  LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart);
628  lpc32xx_uart uart_6;
629  LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart);
630  lpc32xx_i2c i2c_1;
631  LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c);
632  lpc32xx_i2c i2c_2;
633  LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c);
634  lpc32xx_mcpwm mcpwm;
635} lpc32xx_registers;
636
637extern volatile lpc32xx_registers lpc32xx;
638
639/** @} */
640
641#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
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