source: rtems/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h @ f25d31f

4.115
Last change on this file since f25d31f was f25d31f, checked in by Sebastian Huber <sebastian.huber@…>, on 12/17/12 at 15:40:23

bsp/lpc32xx: Add idle thread body

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File size: 5.5 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc32xx
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_LPC32XX_BSP_H
24#define LIBBSP_ARM_LPC32XX_BSP_H
25
26#include <bspopts.h>
27
28#define BSP_FEATURE_IRQ_EXTENSION
29
30#ifndef ASM
31
32#include <rtems.h>
33#include <rtems/console.h>
34#include <rtems/clockdrv.h>
35
36#include <bsp/lpc32xx.h>
37#include <bsp/default-initial-extension.h>
38
39#ifdef __cplusplus
40extern "C" {
41#endif /* __cplusplus */
42
43struct rtems_bsdnet_ifconfig;
44
45/**
46 * @defgroup lpc32xx LPC32XX Support
47 *
48 * @ingroup bsp_kit
49 *
50 * @brief LPC32XX support package.
51 *
52 * @{
53 */
54
55/**
56 * @brief Network driver attach and detach function.
57 */
58int lpc_eth_attach_detach(
59  struct rtems_bsdnet_ifconfig *config,
60  int attaching
61);
62
63/**
64 * @brief Standard network driver attach and detach function.
65 */
66#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
67
68/**
69 * @brief Standard network driver name.
70 */
71#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
72
73/**
74 * @brief Optimized idle task.
75 *
76 * This idle task sets the power mode to idle.  This causes the processor clock
77 * to be stopped, while on-chip peripherals remain active.  Any enabled
78 * interrupt from a peripheral or an external interrupt source will cause the
79 * processor to resume execution.
80 *
81 * To enable the idle task use the following in the system configuration:
82 *
83 * @code
84 * #include <bsp.h>
85 *
86 * #define CONFIGURE_INIT
87 *
88 * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
89 *
90 * #include <confdefs.h>
91 * @endcode
92 */
93void *lpc32xx_idle(uintptr_t ignored);
94
95#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
96
97static inline unsigned lpc32xx_timer(void)
98{
99  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
100
101  return timer->tc;
102}
103
104static inline void lpc32xx_micro_seconds_delay(unsigned us)
105{
106  unsigned start = lpc32xx_timer();
107  unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
108  unsigned elapsed = 0;
109
110  do {
111    elapsed = lpc32xx_timer() - start;
112  } while (elapsed < delay);
113}
114
115#if LPC32XX_OSCILLATOR_MAIN == 13000000U
116  #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
117    (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
118  #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
119    (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0))
120#else
121  #error "unexpected main oscillator frequency"
122#endif
123
124bool lpc32xx_start_pll_setup(
125  uint32_t hclkpll_ctrl,
126  uint32_t hclkdiv_ctrl,
127  bool force
128);
129
130uint32_t lpc32xx_sysclk(void);
131
132uint32_t lpc32xx_hclkpll_clk(void);
133
134uint32_t lpc32xx_periph_clk(void);
135
136uint32_t lpc32xx_hclk(void);
137
138uint32_t lpc32xx_arm_clk(void);
139
140uint32_t lpc32xx_ddram_clk(void);
141
142typedef enum {
143  LPC32XX_NAND_CONTROLLER_NONE,
144  LPC32XX_NAND_CONTROLLER_MLC,
145  LPC32XX_NAND_CONTROLLER_SLC
146} lpc32xx_nand_controller;
147
148void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
149
150void bsp_restart(void *addr);
151
152void *bsp_idle_thread(uintptr_t arg);
153
154#define BSP_IDLE_TASK_BODY bsp_idle_thread
155
156#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
157
158/**
159 * @brief Begin of magic zero area.
160 *
161 * A read from this area returns zero.  Writes have no effect.
162 */
163extern uint32_t lpc32xx_magic_zero_begin [];
164
165/**
166 * @brief End of magic zero area.
167 *
168 * A read from this area returns zero.  Writes have no effect.
169 */
170extern uint32_t lpc32xx_magic_zero_end [];
171
172/**
173 * @brief Size of magic zero area.
174 *
175 * A read from this area returns zero.  Writes have no effect.
176 */
177extern uint32_t lpc32xx_magic_zero_size [];
178
179#ifdef LPC32XX_SCRATCH_AREA_SIZE
180  /**
181   * @rief Scratch area.
182   *
183   * The usage is application specific.
184   */
185  extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]
186    __attribute__((aligned(32)));
187#endif
188
189#define LPC32XX_DO_STOP_GPDMA \
190  do { \
191    if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
192      if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
193        int i = 0; \
194        for (i = 0; i < 8; ++i) { \
195          lpc32xx.dma.channels [i].cfg = 0; \
196        } \
197        lpc32xx.dma.cfg &= ~DMA_CFG_E; \
198      } \
199      LPC32XX_DMACLK_CTRL = 0; \
200    } \
201  } while (0)
202
203#define LPC32XX_DO_STOP_ETHERNET \
204  do { \
205    if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
206      lpc32xx.eth.command = 0x38; \
207      lpc32xx.eth.mac1 = 0xcf00; \
208      lpc32xx.eth.mac1 = 0; \
209      LPC32XX_MAC_CLK_CTRL = 0; \
210    } \
211  } while (0)
212
213#define LPC32XX_DO_STOP_USB \
214  do { \
215    if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
216      LPC32XX_OTG_CLK_CTRL = 0; \
217      LPC32XX_USB_CTRL = 0x80000; \
218    } \
219  } while (0)
220
221#define LPC32XX_DO_RESTART(addr) \
222  do { \
223    ARM_SWITCH_REGISTERS; \
224    rtems_interrupt_level level; \
225    uint32_t ctrl = 0; \
226  \
227    rtems_interrupt_disable(level); \
228  \
229    arm_cp15_data_cache_test_and_clean(); \
230    arm_cp15_instruction_cache_invalidate(); \
231  \
232    ctrl = arm_cp15_get_control(); \
233    ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
234    arm_cp15_set_control(ctrl); \
235  \
236    __asm__ volatile ( \
237      ARM_SWITCH_TO_ARM \
238      "mov pc, %[addr]\n" \
239      ARM_SWITCH_BACK \
240      : ARM_SWITCH_OUTPUT \
241      : [addr] "r" (addr) \
242    ); \
243  } while (0)
244
245/** @} */
246
247/**
248 * @defgroup lpc LPC Support
249 *
250 * @ingroup lpc32xx
251 *
252 * @brief LPC support package.
253 */
254
255#ifdef __cplusplus
256}
257#endif /* __cplusplus */
258
259#endif /* ASM */
260
261#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
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