source: rtems/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h @ 6cfe52f

4.115
Last change on this file since 6cfe52f was 6cfe52f, checked in by Sebastian Huber <sebastian.huber@…>, on 07/25/12 at 13:51:21

bsp/lpc32xx: Add lpc32xx_select_nand_controller()

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Line 
1/**
2 * @file
3 *
4 * @ingroup lpc32xx
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_LPC32XX_BSP_H
24#define LIBBSP_ARM_LPC32XX_BSP_H
25
26#include <bspopts.h>
27
28#include <rtems.h>
29#include <rtems/console.h>
30#include <rtems/clockdrv.h>
31
32#include <bsp/lpc32xx.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif /* __cplusplus */
37
38#define BSP_FEATURE_IRQ_EXTENSION
39
40#ifndef ASM
41
42struct rtems_bsdnet_ifconfig;
43
44/**
45 * @defgroup lpc32xx LPC32XX Support
46 *
47 * @ingroup bsp_kit
48 *
49 * @brief LPC32XX support package.
50 *
51 * @{
52 */
53
54/**
55 * @brief Network driver attach and detach function.
56 */
57int lpc_eth_attach_detach(
58  struct rtems_bsdnet_ifconfig *config,
59  int attaching
60);
61
62/**
63 * @brief Standard network driver attach and detach function.
64 */
65#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
66
67/**
68 * @brief Standard network driver name.
69 */
70#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
71
72/**
73 * @brief Optimized idle task.
74 *
75 * This idle task sets the power mode to idle.  This causes the processor clock
76 * to be stopped, while on-chip peripherals remain active.  Any enabled
77 * interrupt from a peripheral or an external interrupt source will cause the
78 * processor to resume execution.
79 *
80 * To enable the idle task use the following in the system configuration:
81 *
82 * @code
83 * #include <bsp.h>
84 *
85 * #define CONFIGURE_INIT
86 *
87 * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
88 *
89 * #include <confdefs.h>
90 * @endcode
91 */
92void *lpc32xx_idle(uintptr_t ignored);
93
94#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
95
96static inline unsigned lpc32xx_timer(void)
97{
98  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
99
100  return timer->tc;
101}
102
103static inline void lpc32xx_micro_seconds_delay(unsigned us)
104{
105  unsigned start = lpc32xx_timer();
106  unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
107  unsigned elapsed = 0;
108
109  do {
110    elapsed = lpc32xx_timer() - start;
111  } while (elapsed < delay);
112}
113
114#if LPC32XX_OSCILLATOR_MAIN == 13000000U
115  #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
116    (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
117  #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
118    (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(1))
119#else
120  #error "unexpected main oscillator frequency"
121#endif
122
123bool lpc32xx_start_pll_setup(
124  uint32_t hclkpll_ctrl,
125  uint32_t hclkdiv_ctrl,
126  bool force
127);
128
129uint32_t lpc32xx_sysclk(void);
130
131uint32_t lpc32xx_hclkpll_clk(void);
132
133uint32_t lpc32xx_periph_clk(void);
134
135uint32_t lpc32xx_hclk(void);
136
137uint32_t lpc32xx_arm_clk(void);
138
139uint32_t lpc32xx_dram_clk(void);
140
141typedef enum {
142  LPC32XX_NAND_CONTROLLER_NONE,
143  LPC32XX_NAND_CONTROLLER_MLC,
144  LPC32XX_NAND_CONTROLLER_SLC
145} lpc32xx_nand_controller;
146
147void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
148
149void bsp_restart(void *addr);
150
151#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
152
153/**
154 * @brief Begin of magic zero area.
155 *
156 * A read from this area returns zero.  Writes have no effect.
157 */
158extern uint32_t lpc32xx_magic_zero_begin [];
159
160/**
161 * @brief End of magic zero area.
162 *
163 * A read from this area returns zero.  Writes have no effect.
164 */
165extern uint32_t lpc32xx_magic_zero_end [];
166
167/**
168 * @brief Size of magic zero area.
169 *
170 * A read from this area returns zero.  Writes have no effect.
171 */
172extern uint32_t lpc32xx_magic_zero_size [];
173
174#ifdef LPC32XX_SCRATCH_AREA_SIZE
175  /**
176   * @rief Scratch area.
177   *
178   * The usage is application specific.
179   */
180  extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE];
181#endif
182
183#define LPC32XX_DO_STOP_GPDMA \
184  do { \
185    if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
186      if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
187        int i = 0; \
188        for (i = 0; i < 8; ++i) { \
189          lpc32xx.dma.channels [i].cfg = 0; \
190        } \
191        lpc32xx.dma.cfg &= ~DMA_CFG_E; \
192      } \
193      LPC32XX_DMACLK_CTRL = 0; \
194    } \
195  } while (0)
196
197#define LPC32XX_DO_STOP_ETHERNET \
198  do { \
199    if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
200      lpc32xx.eth.command = 0x38; \
201      lpc32xx.eth.mac1 = 0xcf00; \
202      lpc32xx.eth.mac1 = 0; \
203      LPC32XX_MAC_CLK_CTRL = 0; \
204    } \
205  } while (0)
206
207#define LPC32XX_DO_STOP_USB \
208  do { \
209    if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
210      LPC32XX_OTG_CLK_CTRL = 0; \
211      LPC32XX_USB_CTRL = 0x80000; \
212    } \
213  } while (0)
214
215#define LPC32XX_DO_RESTART(addr) \
216  do { \
217    ARM_SWITCH_REGISTERS; \
218    rtems_interrupt_level level; \
219    uint32_t ctrl = 0; \
220  \
221    rtems_interrupt_disable(level); \
222  \
223    arm_cp15_data_cache_test_and_clean(); \
224    arm_cp15_instruction_cache_invalidate(); \
225  \
226    ctrl = arm_cp15_get_control(); \
227    ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
228    arm_cp15_set_control(ctrl); \
229  \
230    __asm__ volatile ( \
231      ARM_SWITCH_TO_ARM \
232      "mov pc, %[addr]\n" \
233      ARM_SWITCH_BACK \
234      : ARM_SWITCH_OUTPUT \
235      : [addr] "r" (addr) \
236    ); \
237  } while (0)
238
239/** @} */
240
241/**
242 * @defgroup lpc LPC Support
243 *
244 * @ingroup lpc32xx
245 *
246 * @brief LPC support package.
247 */
248
249#endif /* ASM */
250
251#ifdef __cplusplus
252}
253#endif /* __cplusplus */
254
255#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
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