1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_lpc32xx |
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5 | * |
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6 | * @brief Global BSP definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_LPC32XX_BSP_H |
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24 | #define LIBBSP_ARM_LPC32XX_BSP_H |
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25 | |
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26 | #include <bspopts.h> |
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27 | |
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28 | #define BSP_FEATURE_IRQ_EXTENSION |
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29 | |
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30 | #ifndef ASM |
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31 | |
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32 | #include <rtems.h> |
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33 | #include <rtems/console.h> |
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34 | #include <rtems/clockdrv.h> |
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35 | |
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36 | #include <bsp/lpc32xx.h> |
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37 | #include <bsp/default-initial-extension.h> |
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38 | |
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39 | #ifdef __cplusplus |
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40 | extern "C" { |
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41 | #endif /* __cplusplus */ |
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42 | |
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43 | struct rtems_bsdnet_ifconfig; |
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44 | |
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45 | /** |
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46 | * @defgroup arm_lpc32xx LPC32XX Support |
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47 | * |
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48 | * @ingroup bsp_arm |
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49 | * |
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50 | * @brief LPC32XX support package. |
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51 | * |
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52 | * @{ |
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53 | */ |
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54 | |
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55 | /** |
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56 | * @brief Network driver attach and detach function. |
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57 | */ |
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58 | int lpc_eth_attach_detach( |
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59 | struct rtems_bsdnet_ifconfig *config, |
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60 | int attaching |
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61 | ); |
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62 | |
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63 | /** |
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64 | * @brief Standard network driver attach and detach function. |
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65 | */ |
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66 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach |
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67 | |
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68 | /** |
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69 | * @brief Standard network driver name. |
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70 | */ |
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71 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" |
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72 | |
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73 | /** |
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74 | * @brief Optimized idle task. |
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75 | * |
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76 | * This idle task sets the power mode to idle. This causes the processor clock |
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77 | * to be stopped, while on-chip peripherals remain active. Any enabled |
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78 | * interrupt from a peripheral or an external interrupt source will cause the |
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79 | * processor to resume execution. |
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80 | * |
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81 | * To enable the idle task use the following in the system configuration: |
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82 | * |
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83 | * @code |
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84 | * #include <bsp.h> |
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85 | * |
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86 | * #define CONFIGURE_INIT |
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87 | * |
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88 | * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle |
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89 | * |
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90 | * #include <confdefs.h> |
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91 | * @endcode |
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92 | */ |
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93 | void *lpc32xx_idle(uintptr_t ignored); |
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94 | |
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95 | #define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1) |
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96 | |
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97 | static inline unsigned lpc32xx_timer(void) |
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98 | { |
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99 | volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; |
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100 | |
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101 | return timer->tc; |
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102 | } |
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103 | |
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104 | static inline void lpc32xx_micro_seconds_delay(unsigned us) |
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105 | { |
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106 | unsigned start = lpc32xx_timer(); |
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107 | unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000); |
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108 | unsigned elapsed = 0; |
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109 | |
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110 | do { |
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111 | elapsed = lpc32xx_timer() - start; |
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112 | } while (elapsed < delay); |
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113 | } |
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114 | |
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115 | #if LPC32XX_OSCILLATOR_MAIN == 13000000U |
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116 | #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \ |
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117 | (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1)) |
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118 | #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \ |
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119 | (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0)) |
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120 | #else |
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121 | #error "unexpected main oscillator frequency" |
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122 | #endif |
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123 | |
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124 | bool lpc32xx_start_pll_setup( |
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125 | uint32_t hclkpll_ctrl, |
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126 | uint32_t hclkdiv_ctrl, |
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127 | bool force |
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128 | ); |
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129 | |
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130 | uint32_t lpc32xx_sysclk(void); |
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131 | |
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132 | uint32_t lpc32xx_hclkpll_clk(void); |
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133 | |
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134 | uint32_t lpc32xx_periph_clk(void); |
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135 | |
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136 | uint32_t lpc32xx_hclk(void); |
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137 | |
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138 | uint32_t lpc32xx_arm_clk(void); |
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139 | |
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140 | uint32_t lpc32xx_ddram_clk(void); |
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141 | |
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142 | typedef enum { |
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143 | LPC32XX_NAND_CONTROLLER_NONE, |
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144 | LPC32XX_NAND_CONTROLLER_MLC, |
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145 | LPC32XX_NAND_CONTROLLER_SLC |
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146 | } lpc32xx_nand_controller; |
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147 | |
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148 | void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller); |
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149 | |
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150 | void bsp_restart(void *addr); |
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151 | |
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152 | void *bsp_idle_thread(uintptr_t arg); |
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153 | |
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154 | #define BSP_IDLE_TASK_BODY bsp_idle_thread |
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155 | |
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156 | #define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5 |
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157 | |
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158 | /** |
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159 | * @brief Begin of magic zero area. |
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160 | * |
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161 | * A read from this area returns zero. Writes have no effect. |
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162 | */ |
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163 | extern uint32_t lpc32xx_magic_zero_begin []; |
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164 | |
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165 | /** |
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166 | * @brief End of magic zero area. |
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167 | * |
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168 | * A read from this area returns zero. Writes have no effect. |
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169 | */ |
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170 | extern uint32_t lpc32xx_magic_zero_end []; |
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171 | |
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172 | /** |
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173 | * @brief Size of magic zero area. |
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174 | * |
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175 | * A read from this area returns zero. Writes have no effect. |
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176 | */ |
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177 | extern uint32_t lpc32xx_magic_zero_size []; |
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178 | |
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179 | #ifdef LPC32XX_SCRATCH_AREA_SIZE |
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180 | /** |
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181 | * @rief Scratch area. |
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182 | * |
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183 | * The usage is application specific. |
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184 | */ |
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185 | extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE] |
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186 | __attribute__((aligned(32))); |
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187 | #endif |
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188 | |
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189 | #define LPC32XX_DO_STOP_GPDMA \ |
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190 | do { \ |
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191 | if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \ |
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192 | if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \ |
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193 | int i = 0; \ |
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194 | for (i = 0; i < 8; ++i) { \ |
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195 | lpc32xx.dma.channels [i].cfg = 0; \ |
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196 | } \ |
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197 | lpc32xx.dma.cfg &= ~DMA_CFG_E; \ |
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198 | } \ |
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199 | LPC32XX_DMACLK_CTRL = 0; \ |
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200 | } \ |
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201 | } while (0) |
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202 | |
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203 | #define LPC32XX_DO_STOP_ETHERNET \ |
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204 | do { \ |
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205 | if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \ |
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206 | lpc32xx.eth.command = 0x38; \ |
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207 | lpc32xx.eth.mac1 = 0xcf00; \ |
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208 | lpc32xx.eth.mac1 = 0; \ |
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209 | LPC32XX_MAC_CLK_CTRL = 0; \ |
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210 | } \ |
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211 | } while (0) |
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212 | |
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213 | #define LPC32XX_DO_STOP_USB \ |
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214 | do { \ |
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215 | if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \ |
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216 | LPC32XX_OTG_CLK_CTRL = 0; \ |
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217 | LPC32XX_USB_CTRL = 0x80000; \ |
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218 | } \ |
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219 | } while (0) |
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220 | |
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221 | #define LPC32XX_DO_RESTART(addr) \ |
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222 | do { \ |
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223 | ARM_SWITCH_REGISTERS; \ |
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224 | rtems_interrupt_level level; \ |
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225 | uint32_t ctrl = 0; \ |
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226 | \ |
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227 | rtems_interrupt_disable(level); \ |
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228 | \ |
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229 | arm_cp15_data_cache_test_and_clean(); \ |
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230 | arm_cp15_instruction_cache_invalidate(); \ |
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231 | \ |
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232 | ctrl = arm_cp15_get_control(); \ |
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233 | ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \ |
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234 | arm_cp15_set_control(ctrl); \ |
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235 | \ |
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236 | __asm__ volatile ( \ |
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237 | ARM_SWITCH_TO_ARM \ |
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238 | "mov pc, %[addr]\n" \ |
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239 | ARM_SWITCH_BACK \ |
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240 | : ARM_SWITCH_OUTPUT \ |
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241 | : [addr] "r" (addr) \ |
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242 | ); \ |
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243 | } while (0) |
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244 | |
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245 | /** @} */ |
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246 | |
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247 | /** |
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248 | * @defgroup lpc LPC Support |
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249 | * |
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250 | * @ingroup arm_lpc32xx |
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251 | * |
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252 | * @brief LPC support package. |
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253 | */ |
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254 | |
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255 | #ifdef __cplusplus |
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256 | } |
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257 | #endif /* __cplusplus */ |
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258 | |
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259 | #endif /* ASM */ |
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260 | |
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261 | #endif /* LIBBSP_ARM_LPC32XX_BSP_H */ |
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