1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_boot |
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5 | * |
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6 | * @brief Boot support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_ARM_LPC32XX_BOOT_H |
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23 | #define LIBBSP_ARM_LPC32XX_BOOT_H |
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24 | |
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25 | #include <stdint.h> |
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26 | |
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27 | #include <bsp/nand-mlc.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif /* __cplusplus */ |
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32 | |
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33 | /** |
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34 | * @defgroup lpc32xx_boot Boot Support |
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35 | * |
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36 | * @ingroup arm_lpc32xx |
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37 | * |
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38 | * @brief Boot support. |
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39 | * |
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40 | * The NXP internal boot program shall be the "stage-0 program". |
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41 | * |
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42 | * The boot program within the first page of the first or second block shall be |
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43 | * "stage-1 program". It will be invoked by the stage-0 program from NXP. |
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44 | * |
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45 | * The program loaded by the stage-1 program will be the "stage-2 program" or the |
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46 | * "boot loader". |
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47 | * |
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48 | * The program loaded by the stage-2 program will be the "stage-3 program" or the |
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49 | * "application". |
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50 | * |
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51 | * The stage-1 program image must have a format specified by NXP. |
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52 | * |
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53 | * The stage-2 and stage-3 program images may have any format. |
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54 | * |
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55 | * @{ |
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56 | */ |
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57 | |
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58 | #define LPC32XX_BOOT_BLOCK_0 0 |
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59 | #define LPC32XX_BOOT_BLOCK_1 1 |
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60 | |
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61 | #define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0 |
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62 | #define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2 |
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63 | #define LPC32XX_BOOT_ICR_LP_4AC_8IF 0xb4 |
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64 | #define LPC32XX_BOOT_ICR_LP_5AC_8IF 0x96 |
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65 | |
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66 | typedef union { |
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67 | struct { |
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68 | uint8_t d0; |
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69 | uint8_t reserved_0 [3]; |
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70 | uint8_t d1; |
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71 | uint8_t reserved_1 [3]; |
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72 | uint8_t d2; |
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73 | uint8_t reserved_2 [3]; |
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74 | uint8_t d3; |
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75 | uint8_t reserved_3 [3]; |
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76 | uint8_t d4; |
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77 | uint8_t reserved_4 [3]; |
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78 | uint8_t d5; |
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79 | uint8_t reserved_5 [3]; |
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80 | uint8_t d6; |
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81 | uint8_t reserved_6 [3]; |
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82 | uint8_t d7; |
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83 | uint8_t reserved_7 [3]; |
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84 | uint8_t d8; |
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85 | uint8_t reserved_8 [3]; |
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86 | uint8_t d9; |
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87 | uint8_t reserved_9 [3]; |
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88 | uint8_t d10; |
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89 | uint8_t reserved_10 [3]; |
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90 | uint8_t d11; |
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91 | uint8_t reserved_11 [3]; |
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92 | uint8_t d12; |
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93 | uint8_t reserved_12 [463]; |
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94 | } field; |
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95 | uint32_t data [MLC_SMALL_DATA_WORD_COUNT]; |
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96 | } lpc32xx_boot_block; |
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97 | |
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98 | void lpc32xx_setup_boot_block( |
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99 | lpc32xx_boot_block *boot_block, |
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100 | uint8_t icr, |
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101 | uint8_t page_count |
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102 | ); |
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103 | |
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104 | void lpc32xx_set_boot_block_bad( |
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105 | lpc32xx_boot_block *boot_block |
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106 | ); |
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107 | |
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108 | /** @} */ |
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109 | |
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110 | #ifdef __cplusplus |
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111 | } |
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112 | #endif /* __cplusplus */ |
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113 | |
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114 | #endif /* LIBBSP_ARM_LPC32XX_BOOT_H */ |
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