1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx |
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5 | * |
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6 | * @brief BSP start EMC static memory configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp/start-config.h> |
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24 | #include <bsp/lpc24xx.h> |
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25 | |
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26 | BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config |
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27 | lpc24xx_start_config_emc_static_chip [] = { |
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28 | #if defined(LPC24XX_EMC_M29W160E) |
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29 | /* |
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30 | * Static Memory 1: Numonyx M29W160EB |
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31 | * |
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32 | * 1 clock cycle = 1/72MHz = 13.9ns |
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33 | */ |
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34 | { |
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35 | .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_1, |
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36 | .config = { |
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37 | /* |
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38 | * 16 bit, page mode disabled, active LOW chip select, extended wait |
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39 | * disabled, writes not protected, byte lane state LOW/LOW (!). |
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40 | */ |
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41 | .config = 0x81, |
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42 | |
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43 | /* 1 clock cycles delay from the chip select 1 to the write enable */ |
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44 | .waitwen = 0, |
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45 | |
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46 | /* |
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47 | * 0 clock cycles delay from the chip select 1 or address change |
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48 | * (whichever is later) to the output enable |
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49 | */ |
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50 | .waitoen = 0, |
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51 | |
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52 | /* 7 clock cycles delay from the chip select 1 to the read access */ |
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53 | .waitrd = 0x6, |
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54 | |
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55 | /* |
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56 | * 32 clock cycles delay for asynchronous page mode sequential accesses |
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57 | */ |
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58 | .waitpage = 0x1f, |
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59 | |
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60 | /* 5 clock cycles delay from the chip select 1 to the write access */ |
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61 | .waitwr = 0x3, |
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62 | |
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63 | /* 16 bus turnaround cycles */ |
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64 | .waitrun = 0xf |
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65 | } |
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66 | } |
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67 | #elif defined(LPC24XX_EMC_M29W320E70) |
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68 | /* Static Memory 0: M29W320E70 */ |
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69 | { |
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70 | .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0, |
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71 | .config = { |
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72 | /* |
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73 | * 16 bit, page mode disabled, active LOW chip select, extended wait |
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74 | * disabled, writes not protected, byte lane state LOW/LOW. |
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75 | */ |
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76 | .config = 0x81, |
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77 | |
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78 | /* 30ns (tWHWL) */ |
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79 | .waitwen = LPC24XX_PS_TO_EMCCLK(30000, 1), |
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80 | |
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81 | /* 0ns */ |
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82 | .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1), |
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83 | |
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84 | /* 70ns (tAVQV, tELQV) */ |
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85 | .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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86 | |
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87 | /* 70ns (tAVQV, tELQV) */ |
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88 | .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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89 | |
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90 | /* max(30ns (tWHWL) + 45ns (tWLWH), 70ns (tAVAV)) */ |
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91 | .waitwr = LPC24XX_PS_TO_EMCCLK(75000, 2), |
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92 | |
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93 | /* 25ns (tEHQZ) */ |
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94 | .waitrun = LPC24XX_PS_TO_EMCCLK(25000, 1) |
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95 | } |
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96 | } |
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97 | #elif defined(LPC24XX_EMC_SST39VF3201) |
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98 | /* Static Memory 0: SST39VF3201 */ |
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99 | { |
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100 | .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0, |
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101 | .config = { |
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102 | /* |
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103 | * 16 bit, page mode disabled, active LOW chip select, extended wait |
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104 | * disabled, writes not protected, byte lane state LOW/LOW. |
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105 | */ |
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106 | .config = 0x81, |
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107 | |
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108 | /* 0ns (tCS, tAS) */ |
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109 | .waitwen = LPC24XX_PS_TO_EMCCLK(0, 1), |
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110 | |
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111 | /* 0ns (tOES) */ |
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112 | .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1), |
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113 | |
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114 | /* 70ns (tRC) */ |
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115 | .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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116 | |
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117 | /* 70ns (tRC) */ |
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118 | .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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119 | |
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120 | /* 20ns (tCHZ, TOHZ) */ |
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121 | .waitwr = LPC24XX_PS_TO_EMCCLK(20000, 2), |
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122 | |
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123 | /* 20ns (tCHZ, TOHZ) */ |
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124 | .waitrun = LPC24XX_PS_TO_EMCCLK(20000, 1) |
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125 | } |
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126 | } |
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127 | #endif |
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128 | }; |
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129 | |
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130 | BSP_START_DATA_SECTION const size_t |
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131 | lpc24xx_start_config_emc_static_chip_count = |
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132 | sizeof(lpc24xx_start_config_emc_static_chip) |
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133 | / sizeof(lpc24xx_start_config_emc_static_chip [0]); |
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