[4f609eec] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc24xx |
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| 5 | * |
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| 6 | * @brief BSP start EMC dynamic memory configuration. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[f7deb58] | 10 | * Copyright (c) 2011-2012 embedded brains GmbH. All rights reserved. |
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[4f609eec] | 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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| 23 | #include <bsp/start-config.h> |
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| 24 | #include <bsp/lpc24xx.h> |
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| 25 | |
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[e4bda046] | 26 | /* |
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| 27 | * FIXME: The NXP example code uses different values for the follwing two |
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| 28 | * defines. In the NXP example code they depend on the EMCCLK. It is unclear |
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| 29 | * how these values are determined. The values from the NXP example code do |
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| 30 | * not work. |
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| 31 | */ |
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| 32 | |
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| 33 | /* Use command delayed strategy */ |
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| 34 | #define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1 |
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| 35 | |
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| 36 | #define LPC24XX_EMCDLYCTL_DEFAULT 0x1112 |
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| 37 | |
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[4a6cc2a] | 38 | BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config |
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[4f609eec] | 39 | lpc24xx_start_config_emc_dynamic [] = { |
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[4a6cc2a] | 40 | #if defined(LPC24XX_EMC_MT48LC4M16A2) |
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[4f609eec] | 41 | /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */ |
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| 42 | { |
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[f7deb58] | 43 | /* 15.6 us */ |
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| 44 | .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16, |
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[4f609eec] | 45 | |
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[e4bda046] | 46 | .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT, |
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[4f609eec] | 47 | |
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| 48 | /* Precharge command period 20 ns */ |
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| 49 | .trp = 1, |
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| 50 | |
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| 51 | /* Active to precharge command period 44 ns */ |
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| 52 | .tras = 3, |
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| 53 | |
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| 54 | /* FIXME */ |
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| 55 | .tsrex = 5, |
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| 56 | |
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| 57 | /* FIXME */ |
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| 58 | .tapr = 2, |
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| 59 | |
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| 60 | /* Data-in to active command period tWR + tRP */ |
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| 61 | .tdal = 4, |
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| 62 | |
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| 63 | /* Write recovery time 15 ns */ |
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| 64 | .twr = 1, |
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| 65 | |
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| 66 | /* Active to active command period 66 ns */ |
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| 67 | .trc = 4, |
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| 68 | |
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| 69 | /* Auto refresh period 66 ns */ |
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| 70 | .trfc = 4, |
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| 71 | |
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| 72 | /* Exit self refresh to active command period 75 ns */ |
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| 73 | .txsr = 5, |
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| 74 | |
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| 75 | /* Active bank a to active bank b command period 15 ns */ |
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| 76 | .trrd = 1, |
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| 77 | |
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| 78 | /* Load mode register to active or refresh command period 2 tCK */ |
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| 79 | .tmrd = 1 |
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| 80 | } |
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[4868c771] | 81 | #elif defined(LPC24XX_EMC_IS42S32800D7) |
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[f7deb58] | 82 | /* Dynamic Memory 0: ISSI IS42S32800D7 */ |
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[4868c771] | 83 | { |
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[f7deb58] | 84 | /* 15.6 us */ |
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| 85 | .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16, |
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[4868c771] | 86 | |
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[e4bda046] | 87 | .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT, |
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[4868c771] | 88 | |
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[f7deb58] | 89 | /* 20ns */ |
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| 90 | .trp = LPC24XX_PS_TO_EMCCLK(20000, 1), |
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[4868c771] | 91 | |
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[f7deb58] | 92 | /* 45ns */ |
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| 93 | .tras = LPC24XX_PS_TO_EMCCLK(45000, 1), |
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[4868c771] | 94 | |
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[f7deb58] | 95 | /* 70ns (tXSR) */ |
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| 96 | .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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[4868c771] | 97 | |
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[f7deb58] | 98 | /* 20ns (tRCD) */ |
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| 99 | .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1), |
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[4868c771] | 100 | |
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| 101 | /* n clock cycles -> 38.8ns >= 35ns */ |
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[f7deb58] | 102 | .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0), |
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[4868c771] | 103 | |
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[f7deb58] | 104 | /* 14ns (tDPL) */ |
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| 105 | .twr = LPC24XX_PS_TO_EMCCLK(14000, 1), |
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[4868c771] | 106 | |
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[f7deb58] | 107 | /* 67.5ns */ |
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| 108 | .trc = LPC24XX_PS_TO_EMCCLK(67500, 1), |
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[4868c771] | 109 | |
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[f7deb58] | 110 | /* 67.5ns (tRC) */ |
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| 111 | .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1), |
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[4868c771] | 112 | |
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[f7deb58] | 113 | /* 70ns */ |
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| 114 | .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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[4868c771] | 115 | |
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[f7deb58] | 116 | /* 14ns */ |
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| 117 | .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1), |
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[4868c771] | 118 | |
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[f7deb58] | 119 | /* 14ns */ |
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[e4bda046] | 120 | .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1), |
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| 121 | |
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| 122 | .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT |
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[4868c771] | 123 | } |
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[4a6cc2a] | 124 | #elif defined(LPC24XX_EMC_W9825G2JB75I) |
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[f7deb58] | 125 | /* Dynamic Memory 0: Winbond W9825G2JB75I */ |
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[4a6cc2a] | 126 | { |
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[f7deb58] | 127 | /* 15.6 us */ |
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| 128 | .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16, |
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[4a6cc2a] | 129 | |
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[e4bda046] | 130 | .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT, |
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[4a6cc2a] | 131 | |
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[f7deb58] | 132 | /* 20ns */ |
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| 133 | .trp = LPC24XX_PS_TO_EMCCLK(20000, 1), |
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[4a6cc2a] | 134 | |
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[f7deb58] | 135 | /* 45ns */ |
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| 136 | .tras = LPC24XX_PS_TO_EMCCLK(45000, 1), |
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[4a6cc2a] | 137 | |
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[f7deb58] | 138 | /* 75ns (tXSR) */ |
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| 139 | .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1), |
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[4a6cc2a] | 140 | |
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[f7deb58] | 141 | /* 20ns (tRCD) */ |
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| 142 | .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1), |
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[4a6cc2a] | 143 | |
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[f7deb58] | 144 | /* tWR + tRP -> 2 * tCK + 20ns */ |
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| 145 | .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0), |
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[4a6cc2a] | 146 | |
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| 147 | /* (n + 1) clock cycles == 2 * tCK */ |
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| 148 | .twr = 1, |
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| 149 | |
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[f7deb58] | 150 | /* 65ns */ |
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| 151 | .trc = LPC24XX_PS_TO_EMCCLK(65000, 1), |
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[4a6cc2a] | 152 | |
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[f7deb58] | 153 | /* 65ns (tRC) */ |
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| 154 | .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1), |
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[4a6cc2a] | 155 | |
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[f7deb58] | 156 | /* 75ns */ |
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| 157 | .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1), |
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[4a6cc2a] | 158 | |
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| 159 | /* (n + 1) clock cycles == 2 * tCK */ |
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| 160 | .trrd = 1, |
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| 161 | |
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| 162 | /* (n + 1) clock cycles == 2 * tCK (tRSC)*/ |
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[e4bda046] | 163 | .tmrd = 1, |
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| 164 | |
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| 165 | .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT |
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[4a6cc2a] | 166 | } |
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[4f609eec] | 167 | #elif defined(LPC24XX_EMC_K4S561632E) |
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| 168 | { |
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| 169 | .refresh = 35, |
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[e4bda046] | 170 | .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT, |
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[4f609eec] | 171 | .trp = 2, |
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| 172 | .tras = 4, |
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| 173 | .tsrex = 5, |
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| 174 | .tapr = 1, |
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| 175 | .tdal = 5, |
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| 176 | .twr = 3, |
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| 177 | .trc = 5, |
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| 178 | .trfc = 5, |
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| 179 | .txsr = 5, |
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| 180 | .trrd = 3, |
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| 181 | .tmrd = 2 |
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| 182 | } |
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[4a6cc2a] | 183 | #elif defined(LPC24XX_EMC_IS42S32800B) |
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[f7deb58] | 184 | { |
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| 185 | /* 15.6us */ |
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| 186 | .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16, |
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| 187 | |
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[e4bda046] | 188 | .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT, |
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[f7deb58] | 189 | |
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| 190 | /* 20ns */ |
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| 191 | .trp = LPC24XX_PS_TO_EMCCLK(20000, 1), |
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| 192 | |
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| 193 | /* 45ns */ |
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| 194 | .tras = LPC24XX_PS_TO_EMCCLK(45000, 1), |
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| 195 | |
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| 196 | /* 70ns (tRC) */ |
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| 197 | .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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| 198 | |
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| 199 | /* FIXME */ |
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| 200 | .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1), |
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| 201 | |
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| 202 | /* tWR + tRP -> 2 * tCK + 20ns */ |
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| 203 | .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0), |
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| 204 | |
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| 205 | /* (n + 1) clock cycles == 2 * tCK */ |
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| 206 | .twr = 1, |
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| 207 | |
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| 208 | /* 70ns */ |
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| 209 | .trc = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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| 210 | |
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| 211 | /* 70ns */ |
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| 212 | .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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| 213 | |
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| 214 | /* 70ns (tRC) */ |
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| 215 | .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1), |
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| 216 | |
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| 217 | /* 14ns */ |
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| 218 | .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1), |
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| 219 | |
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| 220 | /* (n + 1) clock cycles == 2 * tCK */ |
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| 221 | .tmrd = 1, |
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| 222 | |
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[e4bda046] | 223 | .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT |
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[f7deb58] | 224 | } |
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[4f609eec] | 225 | #endif |
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| 226 | }; |
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| 227 | |
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[4a6cc2a] | 228 | BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config |
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[4f609eec] | 229 | lpc24xx_start_config_emc_dynamic_chip [] = { |
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[4a6cc2a] | 230 | #if defined(LPC24XX_EMC_MT48LC4M16A2) |
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[4f609eec] | 231 | { |
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| 232 | .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0, |
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| 233 | |
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| 234 | /* |
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| 235 | * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected |
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[4a6cc2a] | 236 | * writes. 4 banks, 12 row lines, 8 column lines. |
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[4f609eec] | 237 | */ |
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| 238 | .config = 0x280, |
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| 239 | |
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| 240 | .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0), |
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| 241 | .mode = 0xa0000000 | (0x23 << (1 + 2 + 8)) |
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| 242 | } |
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[4868c771] | 243 | #elif defined(LPC24XX_EMC_W9825G2JB75I) \ |
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| 244 | || defined(LPC24XX_EMC_IS42S32800D7) |
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[4a6cc2a] | 245 | { |
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| 246 | .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0, |
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| 247 | |
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| 248 | /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */ |
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[4868c771] | 249 | .config = 0x4480, |
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[4a6cc2a] | 250 | |
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| 251 | /* RAS based on tRCD = 20ns */ |
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| 252 | .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0), |
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| 253 | |
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[4868c771] | 254 | /* CAS 2, burst length 4 */ |
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| 255 | .mode = 0xa0000000 | (0x22 << (2 + 2 + 9)) |
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[4a6cc2a] | 256 | } |
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[4f609eec] | 257 | #elif defined(LPC24XX_EMC_K4S561632E) |
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| 258 | { |
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| 259 | .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0, |
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| 260 | .config = 0x680, |
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| 261 | .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0), |
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| 262 | .mode = 0xa0000000 | (0x33 << 12) |
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| 263 | } |
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[4a6cc2a] | 264 | #elif defined(LPC24XX_EMC_IS42S32800B) |
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| 265 | { |
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| 266 | .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0, |
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| 267 | |
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| 268 | /* 256MBit, 8Mx32, 4 banks, row = 12, column = 9, RBC */ |
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| 269 | .config = 0x4480, |
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| 270 | |
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| 271 | #if LPC24XX_EMCCLK == 72000000U |
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| 272 | .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0), |
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| 273 | .mode = 0xa0000000 | (0x32 << (2 + 2 + 9)) |
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| 274 | #elif LPC24XX_EMCCLK == 60000000U |
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| 275 | .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0), |
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| 276 | .mode = 0xa0000000 | (0x22 << (2 + 2 + 9)) |
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| 277 | #else |
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| 278 | #error "unexpected EMCCLK" |
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| 279 | #endif |
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| 280 | } |
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[4f609eec] | 281 | #endif |
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| 282 | }; |
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| 283 | |
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[4a6cc2a] | 284 | BSP_START_DATA_SECTION const size_t |
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[4f609eec] | 285 | lpc24xx_start_config_emc_dynamic_chip_count = |
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| 286 | sizeof(lpc24xx_start_config_emc_dynamic_chip) |
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| 287 | / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]); |
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