source: rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c @ e4bda046

4.115
Last change on this file since e4bda046 was e4bda046, checked in by Sebastian Huber <sebastian.huber@…>, on 06/11/12 at 12:48:42

bsp/lpc24xx: Simplify EMCDLYCTL handling

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File size: 6.8 KB
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[4f609eec]1/**
2 * @file
3 *
4 * @ingroup lpc24xx
5 *
6 * @brief BSP start EMC dynamic memory configuration.
7 */
8
9/*
[f7deb58]10 * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
[4f609eec]11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <bsp/start-config.h>
24#include <bsp/lpc24xx.h>
25
[e4bda046]26/*
27 * FIXME: The NXP example code uses different values for the follwing two
28 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
29 * how these values are determined.  The values from the NXP example code do
30 * not work.
31 */
32
33/* Use command delayed strategy */
34#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
35
36#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
37
[4a6cc2a]38BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
[4f609eec]39  lpc24xx_start_config_emc_dynamic [] = {
[4a6cc2a]40#if defined(LPC24XX_EMC_MT48LC4M16A2)
[4f609eec]41  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
42  {
[f7deb58]43    /* 15.6 us */
44    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
[4f609eec]45
[e4bda046]46    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
[4f609eec]47
48    /* Precharge command period 20 ns */
49    .trp = 1,
50
51    /* Active to precharge command period 44 ns */
52    .tras = 3,
53
54    /* FIXME */
55    .tsrex = 5,
56
57    /* FIXME */
58    .tapr = 2,
59
60    /* Data-in to active command period tWR + tRP */
61    .tdal = 4,
62
63    /* Write recovery time 15 ns */
64    .twr = 1,
65
66    /* Active to active command period 66 ns */
67    .trc = 4,
68
69    /* Auto refresh period 66 ns */
70    .trfc = 4,
71
72    /* Exit self refresh to active command period 75 ns */
73    .txsr = 5,
74
75    /* Active bank a to active bank b command period 15 ns */
76    .trrd = 1,
77
78    /* Load mode register to active or refresh command period 2 tCK */
79    .tmrd = 1
80  }
[4868c771]81#elif defined(LPC24XX_EMC_IS42S32800D7)
[f7deb58]82  /* Dynamic Memory 0: ISSI IS42S32800D7 */
[4868c771]83  {
[f7deb58]84    /* 15.6 us */
85    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
[4868c771]86
[e4bda046]87    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
[4868c771]88
[f7deb58]89    /* 20ns */
90    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
[4868c771]91
[f7deb58]92    /* 45ns */
93    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
[4868c771]94
[f7deb58]95    /* 70ns (tXSR) */
96    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
[4868c771]97
[f7deb58]98    /* 20ns (tRCD) */
99    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
[4868c771]100
101    /* n clock cycles -> 38.8ns >= 35ns */
[f7deb58]102    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
[4868c771]103
[f7deb58]104    /* 14ns (tDPL) */
105    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
[4868c771]106
[f7deb58]107    /* 67.5ns */
108    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
[4868c771]109
[f7deb58]110    /* 67.5ns (tRC) */
111    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
[4868c771]112
[f7deb58]113    /* 70ns */
114    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
[4868c771]115
[f7deb58]116    /* 14ns */
117    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
[4868c771]118
[f7deb58]119    /* 14ns */
[e4bda046]120    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
121
122    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
[4868c771]123  }
[4a6cc2a]124#elif defined(LPC24XX_EMC_W9825G2JB75I)
[f7deb58]125  /* Dynamic Memory 0: Winbond W9825G2JB75I */
[4a6cc2a]126  {
[f7deb58]127    /* 15.6 us */
128    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
[4a6cc2a]129
[e4bda046]130    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
[4a6cc2a]131
[f7deb58]132    /* 20ns */
133    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
[4a6cc2a]134
[f7deb58]135    /* 45ns */
136    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
[4a6cc2a]137
[f7deb58]138    /* 75ns (tXSR) */
139    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
[4a6cc2a]140
[f7deb58]141    /* 20ns (tRCD) */
142    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
[4a6cc2a]143
[f7deb58]144    /* tWR + tRP -> 2 * tCK + 20ns */
145    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
[4a6cc2a]146
147    /* (n + 1) clock cycles == 2 * tCK */
148    .twr = 1,
149
[f7deb58]150    /* 65ns */
151    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
[4a6cc2a]152
[f7deb58]153    /* 65ns (tRC) */
154    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
[4a6cc2a]155
[f7deb58]156    /* 75ns */
157    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
[4a6cc2a]158
159    /* (n + 1) clock cycles == 2 * tCK */
160    .trrd = 1,
161
162    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
[e4bda046]163    .tmrd = 1,
164
165    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
[4a6cc2a]166  }
[4f609eec]167#elif defined(LPC24XX_EMC_K4S561632E)
168  {
169    .refresh = 35,
[e4bda046]170    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
[4f609eec]171    .trp = 2,
172    .tras = 4,
173    .tsrex = 5,
174    .tapr = 1,
175    .tdal = 5,
176    .twr = 3,
177    .trc = 5,
178    .trfc = 5,
179    .txsr = 5,
180    .trrd = 3,
181    .tmrd = 2
182  }
[4a6cc2a]183#elif defined(LPC24XX_EMC_IS42S32800B)
[f7deb58]184  {
185    /* 15.6us */
186    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
187
[e4bda046]188    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
[f7deb58]189
190    /* 20ns */
191    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
192
193    /* 45ns */
194    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
195
196    /* 70ns (tRC) */
197    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
198
199    /* FIXME */
200    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
201
202    /* tWR + tRP -> 2 * tCK + 20ns */
203    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
204
205    /* (n + 1) clock cycles == 2 * tCK */
206    .twr = 1,
207
208    /* 70ns */
209    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
210
211    /* 70ns */
212    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
213
214    /* 70ns (tRC) */
215    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
216
217    /* 14ns */
218    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
219
220    /* (n + 1) clock cycles == 2 * tCK */
221    .tmrd = 1,
222
[e4bda046]223    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
[f7deb58]224  }
[4f609eec]225#endif
226};
227
[4a6cc2a]228BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
[4f609eec]229  lpc24xx_start_config_emc_dynamic_chip [] = {
[4a6cc2a]230#if defined(LPC24XX_EMC_MT48LC4M16A2)
[4f609eec]231  {
232    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
233
234    /*
235     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
[4a6cc2a]236     * writes.  4 banks, 12 row lines, 8 column lines.
[4f609eec]237     */
238    .config = 0x280,
239
240    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
241    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
242  }
[4868c771]243#elif defined(LPC24XX_EMC_W9825G2JB75I) \
244  || defined(LPC24XX_EMC_IS42S32800D7)
[4a6cc2a]245  {
246    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
247
248    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
[4868c771]249    .config = 0x4480,
[4a6cc2a]250
251    /* RAS based on tRCD = 20ns */
252    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
253
[4868c771]254    /* CAS 2, burst length 4 */
255    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
[4a6cc2a]256  }
[4f609eec]257#elif defined(LPC24XX_EMC_K4S561632E)
258  {
259    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
260    .config = 0x680,
261    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
262    .mode = 0xa0000000 | (0x33 << 12)
263  }
[4a6cc2a]264#elif defined(LPC24XX_EMC_IS42S32800B)
265  {
266    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
267
268    /* 256MBit, 8Mx32, 4 banks, row = 12, column = 9, RBC */
269    .config = 0x4480,
270
271    #if LPC24XX_EMCCLK == 72000000U
272      .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
273      .mode = 0xa0000000 | (0x32 << (2 + 2 + 9))
274    #elif LPC24XX_EMCCLK == 60000000U
275      .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
276      .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
277    #else
278      #error "unexpected EMCCLK"
279    #endif
280  }
[4f609eec]281#endif
282};
283
[4a6cc2a]284BSP_START_DATA_SECTION const size_t
[4f609eec]285  lpc24xx_start_config_emc_dynamic_chip_count =
286    sizeof(lpc24xx_start_config_emc_dynamic_chip)
287      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
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