source: rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c @ fb0584f

4.115
Last change on this file since fb0584f was fb0584f, checked in by Sebastian Huber <sebastian.huber@…>, on May 3, 2013 at 8:39:26 AM

bsps/arm: Move implementation to inline functions

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1/**
2 * @file
3 *
4 * @ingroup lpc24xx
5 *
6 * @brief Startup code.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <bsp.h>
24#include <bsp/io.h>
25#include <bsp/start.h>
26#include <bsp/lpc24xx.h>
27#include <bsp/lpc-emc.h>
28#include <bsp/start-config.h>
29
30static BSP_START_TEXT_SECTION void lpc24xx_cpu_delay(unsigned ticks)
31{
32  unsigned i = 0;
33
34  /* One loop execution needs four instructions */
35  ticks /= 4;
36
37  for (i = 0; i <= ticks; ++i) {
38    __asm__ volatile ("nop");
39  }
40}
41
42static BSP_START_TEXT_SECTION void lpc24xx_udelay(unsigned us)
43{
44  lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000));
45}
46
47static BSP_START_TEXT_SECTION void lpc24xx_init_pinsel(void)
48{
49  lpc24xx_pin_config(
50    &lpc24xx_start_config_pinsel [0],
51    LPC24XX_PIN_SET_FUNCTION
52  );
53}
54
55static BSP_START_TEXT_SECTION void lpc24xx_init_emc_static(void)
56{
57  size_t i = 0;
58  size_t chip_count = lpc24xx_start_config_emc_static_chip_count;
59
60  for (i = 0; i < chip_count; ++i) {
61    const lpc24xx_emc_static_chip_config *chip_config =
62      &lpc24xx_start_config_emc_static_chip [i];
63    lpc24xx_emc_static_chip_config chip_config_on_stack;
64    size_t config_size = sizeof(chip_config_on_stack.config);
65
66    bsp_start_memcpy(
67      (int *) &chip_config_on_stack.config,
68      (const int *) &chip_config->config,
69      config_size
70    );
71    bsp_start_memcpy(
72      (int *) chip_config->chip_select,
73      (const int *) &chip_config_on_stack.config,
74      config_size
75    );
76  }
77}
78
79static BSP_START_TEXT_SECTION void lpc24xx_init_emc_dynamic(void)
80{
81  size_t chip_count = lpc24xx_start_config_emc_dynamic_chip_count;
82
83  if (chip_count > 0) {
84    bool do_initialization = true;
85    size_t i = 0;
86
87    for (i = 0; do_initialization && i < chip_count; ++i) {
88      const lpc24xx_emc_dynamic_chip_config *chip_cfg =
89        &lpc24xx_start_config_emc_dynamic_chip [i];
90      volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
91
92      do_initialization = (chip_select->config & EMC_DYN_CFG_B) == 0;
93    }
94
95    if (do_initialization) {
96      volatile lpc_emc *emc = (volatile lpc_emc *) EMC_BASE_ADDR;
97      const lpc24xx_emc_dynamic_config *cfg =
98        &lpc24xx_start_config_emc_dynamic [0];
99      uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS;
100
101      #ifdef ARM_MULTILIB_ARCH_V7M
102        volatile lpc17xx_scb *scb = &LPC17XX_SCB;
103
104        /* Delay control */
105        scb->emcdlyctl = cfg->emcdlyctl;
106      #endif
107
108      emc->dynamicreadconfig = cfg->readconfig;
109
110      /* Timings */
111      emc->dynamictrp = cfg->trp;
112      emc->dynamictras = cfg->tras;
113      emc->dynamictsrex = cfg->tsrex;
114      emc->dynamictapr = cfg->tapr;
115      emc->dynamictdal = cfg->tdal;
116      emc->dynamictwr = cfg->twr;
117      emc->dynamictrc = cfg->trc;
118      emc->dynamictrfc = cfg->trfc;
119      emc->dynamictxsr = cfg->txsr;
120      emc->dynamictrrd = cfg->trrd;
121      emc->dynamictmrd = cfg->tmrd;
122
123      /* NOP period */
124      emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP;
125      lpc24xx_udelay(200);
126
127      /* Precharge */
128      emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL;
129      emc->dynamicrefresh = 1;
130
131      /*
132       * Perform several refresh cycles with a memory refresh every 16 AHB
133       * clock cycles.  Wait until eight SDRAM refresh cycles have occurred
134       * (128 AHB clock cycles).
135       */
136      lpc24xx_cpu_delay(128);
137
138      /* Refresh timing */
139      emc->dynamicrefresh = cfg->refresh;
140      lpc24xx_cpu_delay(128);
141
142      for (i = 0; i < chip_count; ++i) {
143        const lpc24xx_emc_dynamic_chip_config *chip_cfg =
144          &lpc24xx_start_config_emc_dynamic_chip [i];
145        volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
146        uint32_t config = chip_cfg->config;
147
148        /* Chip select */
149        chip_select->config = config;
150        chip_select->rascas = chip_cfg->rascas;
151
152        /* Set modes */
153        emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE;
154        *(volatile uint32_t *)(chip_cfg->address + chip_cfg->mode);
155
156        /* Enable buffer */
157        chip_select->config = config | EMC_DYN_CFG_B;
158      }
159
160      emc->dynamiccontrol = 0;
161    }
162  }
163}
164
165static BSP_START_TEXT_SECTION void lpc24xx_init_main_oscillator(void)
166{
167  #ifdef ARM_MULTILIB_ARCH_V4
168    if ((SCS & 0x40) == 0) {
169      SCS |= 0x20;
170      while ((SCS & 0x40) == 0) {
171        /* Wait */
172      }
173    }
174  #else
175    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
176
177    if ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
178      scb->scs |= LPC17XX_SCB_SCS_OSC_ENABLE;
179      while ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
180        /* Wait */
181      }
182    }
183  #endif
184}
185
186#ifdef ARM_MULTILIB_ARCH_V4
187
188static BSP_START_TEXT_SECTION void lpc24xx_pll_config(
189  uint32_t val
190)
191{
192  PLLCON = val;
193  PLLFEED = 0xaa;
194  PLLFEED = 0x55;
195}
196
197/**
198 * @brief Sets the Phase Locked Loop (PLL).
199 *
200 * All parameter values are the actual register field values.
201 *
202 * @param clksrc Selects the clock source for the PLL.
203 *
204 * @param nsel Selects PLL pre-divider value (sometimes named psel).
205 *
206 * @param msel Selects PLL multiplier value.
207 *
208 * @param cclksel Selects the divide value for creating the CPU clock (CCLK)
209 * from the PLL output.
210 */
211static BSP_START_TEXT_SECTION void lpc24xx_set_pll(
212  unsigned clksrc,
213  unsigned nsel,
214  unsigned msel,
215  unsigned cclksel
216)
217{
218  uint32_t pllstat = PLLSTAT;
219  uint32_t pllcfg = SET_PLLCFG_NSEL(0, nsel) | SET_PLLCFG_MSEL(0, msel);
220  uint32_t clksrcsel = SET_CLKSRCSEL_CLKSRC(0, clksrc);
221  uint32_t cclkcfg = SET_CCLKCFG_CCLKSEL(0, cclksel | 1);
222  bool pll_enabled = (pllstat & PLLSTAT_PLLE) != 0;
223
224  /* Disconnect PLL if necessary */
225  if ((pllstat & PLLSTAT_PLLC) != 0) {
226    if (pll_enabled) {
227      /* Check if we run already with the desired settings */
228      if (PLLCFG == pllcfg && CLKSRCSEL == clksrcsel && CCLKCFG == cclkcfg) {
229        /* Nothing to do */
230        return;
231      }
232      lpc24xx_pll_config(PLLCON_PLLE);
233    } else {
234      lpc24xx_pll_config(0);
235    }
236  }
237
238  /* Set CPU clock divider to a reasonable save value */
239  CCLKCFG = 0;
240
241  /* Disable PLL if necessary */
242  if (pll_enabled) {
243    lpc24xx_pll_config(0);
244  }
245
246  /* Select clock source */
247  CLKSRCSEL = clksrcsel;
248
249  /* Set PLL Configuration Register */
250  PLLCFG = pllcfg;
251
252  /* Enable PLL */
253  lpc24xx_pll_config(PLLCON_PLLE);
254
255  /* Wait for lock */
256  while ((PLLSTAT & PLLSTAT_PLOCK) == 0) {
257    /* Wait */
258  }
259
260  /* Set CPU clock divider and ensure that we have an odd value */
261  CCLKCFG = cclkcfg;
262
263  /* Connect PLL */
264  lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC);
265}
266
267#else /* ARM_MULTILIB_ARCH_V4 */
268
269static BSP_START_TEXT_SECTION void lpc17xx_pll_config(
270  volatile lpc17xx_pll *pll,
271  uint32_t val
272)
273{
274  pll->con = val;
275  pll->feed = 0xaa;
276  pll->feed = 0x55;
277}
278
279static BSP_START_TEXT_SECTION void lpc17xx_set_pll(
280  unsigned msel,
281  unsigned psel,
282  unsigned cclkdiv
283)
284{
285  volatile lpc17xx_scb *scb = &LPC17XX_SCB;
286  volatile lpc17xx_pll *pll = &scb->pll_0;
287  uint32_t pllcfg = LPC17XX_PLL_SEL_MSEL(msel)
288    | LPC17XX_PLL_SEL_PSEL(psel);
289  uint32_t pllstat = LPC17XX_PLL_STAT_PLLE
290    | LPC17XX_PLL_STAT_PLOCK | pllcfg;
291  uint32_t cclksel_cclkdiv = LPC17XX_SCB_CCLKSEL_CCLKDIV(cclkdiv);
292  uint32_t cclksel = LPC17XX_SCB_CCLKSEL_CCLKSEL | cclksel_cclkdiv;
293
294  if (
295    pll->stat != pllstat
296      || scb->cclksel != cclksel
297      || scb->clksrcsel != LPC17XX_SCB_CLKSRCSEL_CLKSRC
298  ) {
299    /* Use SYSCLK for CCLK */
300    scb->cclksel = LPC17XX_SCB_CCLKSEL_CCLKDIV(1);
301
302    /* Turn off USB */
303    scb->usbclksel = 0;
304
305    /* Disable PLL */
306    lpc17xx_pll_config(pll, 0);
307
308    /* Select main oscillator as clock source */
309    scb->clksrcsel = LPC17XX_SCB_CLKSRCSEL_CLKSRC;
310
311    /* Set PLL configuration */
312    pll->cfg = pllcfg;
313
314    /* Set the CCLK, PCLK and EMCCLK divider */
315    scb->cclksel = cclksel_cclkdiv;
316    scb->pclksel = LPC17XX_SCB_PCLKSEL_PCLKDIV(cclkdiv * LPC24XX_PCLKDIV);
317    scb->emcclksel = LPC24XX_EMCCLKDIV == 1 ? 0 : LPC17XX_SCB_EMCCLKSEL_EMCDIV;
318
319    /* Enable PLL */
320    lpc17xx_pll_config(pll, LPC17XX_PLL_CON_PLLE);
321
322    /* Wait for lock */
323    while ((pll->stat & LPC17XX_PLL_STAT_PLOCK) == 0) {
324      /* Wait */
325    }
326
327    /* Use the PLL clock */
328    scb->cclksel = cclksel;
329  }
330}
331
332#endif /* ARM_MULTILIB_ARCH_V4 */
333
334static BSP_START_TEXT_SECTION void lpc24xx_init_pll(void)
335{
336  #ifdef ARM_MULTILIB_ARCH_V4
337    #if LPC24XX_OSCILLATOR_MAIN == 12000000U
338      #if LPC24XX_CCLK == 72000000U
339        lpc24xx_set_pll(1, 0, 11, 3);
340      #elif LPC24XX_CCLK == 51612800U
341        lpc24xx_set_pll(1, 30, 399, 5);
342      #else
343        #error "unexpected CCLK"
344      #endif
345    #elif LPC24XX_OSCILLATOR_MAIN == 3686400U
346      #if LPC24XX_CCLK == 58982400U
347        lpc24xx_set_pll(1, 0, 47, 5);
348      #else
349        #error "unexpected CCLK"
350      #endif
351    #else
352      #error "unexpected main oscillator frequency"
353    #endif
354  #else
355    #if LPC24XX_OSCILLATOR_MAIN == 12000000U
356      #if LPC24XX_CCLK == 120000000U
357        lpc17xx_set_pll(9, 0, 1);
358      #elif LPC24XX_CCLK == 96000000U
359        lpc17xx_set_pll(7, 0, 1);
360      #elif LPC24XX_CCLK == 72000000U
361        lpc17xx_set_pll(5, 1, 1);
362      #elif LPC24XX_CCLK == 48000000U
363        lpc17xx_set_pll(3, 1, 1);
364      #else
365        #error "unexpected CCLK"
366      #endif
367    #else
368      #error "unexpected main oscillator frequency"
369    #endif
370  #endif
371}
372
373static BSP_START_TEXT_SECTION void lpc24xx_init_memory_map(void)
374{
375  #ifdef ARM_MULTILIB_ARCH_V4
376    /* Re-map interrupt vectors to internal RAM */
377    MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
378  #else
379    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
380
381    scb->memmap = LPC17XX_SCB_MEMMAP_MAP;
382  #endif
383
384  /* Use normal memory map */
385  EMC_CTRL &= ~0x2U;
386}
387
388static BSP_START_TEXT_SECTION void lpc24xx_init_memory_accelerator(void)
389{
390  #ifdef ARM_MULTILIB_ARCH_V4
391    /* Fully enable memory accelerator module functions (MAM) */
392    MAMCR = 0;
393    #if LPC24XX_CCLK <= 20000000U
394      MAMTIM = 0x1;
395    #elif LPC24XX_CCLK <= 40000000U
396      MAMTIM = 0x2;
397    #elif LPC24XX_CCLK <= 60000000U
398      MAMTIM = 0x3;
399    #else
400      MAMTIM = 0x4;
401    #endif
402    MAMCR = 0x2;
403
404    /* Enable fast IO for ports 0 and 1 */
405    SCS |= 0x1;
406  #else
407    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
408
409    #if LPC24XX_CCLK <= 20000000U
410      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x0);
411    #elif LPC24XX_CCLK <= 40000000U
412      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x1);
413    #elif LPC24XX_CCLK <= 60000000U
414      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x2);
415    #elif LPC24XX_CCLK <= 80000000U
416      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x3);
417    #elif LPC24XX_CCLK <= 100000000U
418      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x4);
419    #else
420      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x5);
421    #endif
422  #endif
423}
424
425static BSP_START_TEXT_SECTION void lpc24xx_stop_gpdma(void)
426{
427  #ifdef LPC24XX_STOP_GPDMA
428    #ifdef ARM_MULTILIB_ARCH_V4
429      bool has_power = (PCONP & PCONP_GPDMA) != 0;
430    #else
431      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
432      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_GPDMA) != 0;
433    #endif
434
435    if (has_power) {
436      GPDMA_CONFIG = 0;
437
438      #ifdef ARM_MULTILIB_ARCH_V4
439        PCONP &= ~PCONP_GPDMA;
440      #else
441        scb->pconp &= ~LPC17XX_SCB_PCONP_GPDMA;
442      #endif
443    }
444  #endif
445}
446
447static BSP_START_TEXT_SECTION void lpc24xx_stop_ethernet(void)
448{
449  #ifdef LPC24XX_STOP_ETHERNET
450    #ifdef ARM_MULTILIB_ARCH_V4
451      bool has_power = (PCONP & PCONP_ETHERNET) != 0;
452    #else
453      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
454      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_ENET) != 0;
455    #endif
456
457    if (has_power) {
458      MAC_COMMAND = 0x38;
459      MAC_MAC1 = 0xcf00;
460      MAC_MAC1 = 0;
461
462      #ifdef ARM_MULTILIB_ARCH_V4
463        PCONP &= ~PCONP_ETHERNET;
464      #else
465        scb->pconp &= ~LPC17XX_SCB_PCONP_ENET;
466      #endif
467    }
468  #endif
469}
470
471static BSP_START_TEXT_SECTION void lpc24xx_stop_usb(void)
472{
473  #ifdef LPC24XX_STOP_USB
474    #ifdef ARM_MULTILIB_ARCH_V4
475      bool has_power = (PCONP & PCONP_USB) != 0;
476    #else
477      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
478      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_USB) != 0;
479    #endif
480
481    if (has_power) {
482      OTG_CLK_CTRL = 0;
483
484      #ifdef ARM_MULTILIB_ARCH_V4
485        PCONP &= ~PCONP_USB;
486      #else
487        scb->pconp &= ~LPC17XX_SCB_PCONP_USB;
488        scb->usbclksel = 0;
489      #endif
490    }
491  #endif
492}
493
494static BSP_START_TEXT_SECTION void lpc24xx_init_mpu(void)
495{
496  #ifdef ARM_MULTILIB_ARCH_V7M
497    volatile ARMV7M_MPU *mpu = _ARMV7M_MPU;
498    size_t region_count = lpc24xx_start_config_mpu_region_count;
499    size_t i = 0;
500
501    for (i = 0; i < region_count; ++i) {
502      mpu->rbar = lpc24xx_start_config_mpu_region [i].rbar;
503      mpu->rasr = lpc24xx_start_config_mpu_region [i].rasr;
504    }
505
506    if (region_count > 0) {
507      mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE;
508    }
509  #endif
510}
511
512BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
513{
514  lpc24xx_init_main_oscillator();
515  lpc24xx_init_pll();
516  lpc24xx_init_pinsel();
517  lpc24xx_init_emc_static();
518}
519
520BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
521{
522  lpc24xx_init_memory_map();
523  lpc24xx_init_memory_accelerator();
524  lpc24xx_init_emc_dynamic();
525  lpc24xx_init_mpu();
526  lpc24xx_stop_gpdma();
527  lpc24xx_stop_ethernet();
528  lpc24xx_stop_usb();
529  bsp_start_copy_sections();
530  bsp_start_clear_bss();
531
532  /* At this point we can use objects outside the .start section */
533}
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