1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx |
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5 | * |
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6 | * @brief Startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008, 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #include <stdbool.h> |
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23 | |
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24 | #include <bspopts.h> |
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25 | #include <bsp/start.h> |
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26 | #include <bsp/lpc24xx.h> |
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27 | #include <bsp/linker-symbols.h> |
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28 | |
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29 | #ifdef LPC24XX_EMC_MICRON |
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30 | static void __attribute__((section(".bsp_start"))) lpc24xx_ram_test_32(void) |
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31 | { |
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32 | #ifdef LPC24XX_EMC_TEST |
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33 | int *begin = (int *) 0xa0000000; |
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34 | const int *end = (const int *) 0xa0800000; |
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35 | int *out = begin; |
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36 | |
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37 | while (out != end) { |
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38 | *out = (int) out; |
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39 | ++out; |
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40 | } |
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41 | |
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42 | out = begin; |
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43 | while (out != end) { |
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44 | if (*out != (int) out) { |
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45 | while (true) { |
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46 | /* Do nothing */ |
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47 | } |
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48 | } |
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49 | ++out; |
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50 | } |
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51 | #endif |
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52 | } |
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53 | |
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54 | static void __attribute__((section(".bsp_start"))) lpc24xx_cpu_delay( |
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55 | unsigned ticks |
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56 | ) |
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57 | { |
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58 | unsigned i = 0; |
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59 | |
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60 | /* One loop execution needs four instructions */ |
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61 | ticks /= 4; |
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62 | |
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63 | for (i = 0; i <= ticks; ++i) { |
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64 | asm volatile ("nop"); |
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65 | } |
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66 | } |
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67 | #endif |
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68 | |
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69 | /** |
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70 | * @brief EMC initialization hook 0. |
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71 | */ |
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72 | static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_0(void) |
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73 | { |
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74 | #ifdef LPC24XX_EMC_NUMONYX |
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75 | /* |
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76 | * Static Memory 1: Numonyx M29W160EB |
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77 | * |
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78 | * 1 clock cycle = 1/72MHz = 13.9ns |
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79 | * |
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80 | * We cannot use an initializer since this will result in the usage of the |
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81 | * read-only data section which is not available here. |
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82 | */ |
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83 | lpc24xx_emc_static numonyx; |
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84 | |
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85 | /* |
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86 | * 16 bit, page mode disabled, active LOW chip select, extended wait |
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87 | * disabled, writes not protected, byte lane state LOW/LOW (!). |
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88 | */ |
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89 | numonyx.cfg = 0x81; |
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90 | |
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91 | /* 1 clock cycles delay from the chip select 1 to the write enable */ |
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92 | numonyx.waitwen = 0; |
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93 | |
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94 | /* |
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95 | * 0 clock cycles delay from the chip select 1 or address change |
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96 | * (whichever is later) to the output enable |
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97 | */ |
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98 | numonyx.waitoen = 0; |
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99 | |
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100 | /* 7 clock cycles delay from the chip select 1 to the read access */ |
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101 | numonyx.waitrd = 0x6; |
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102 | |
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103 | /* |
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104 | * 32 clock cycles delay for asynchronous page mode sequential accesses |
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105 | */ |
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106 | numonyx.waitpage = 0x1f; |
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107 | |
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108 | /* 5 clock cycles delay from the chip select 1 to the write access */ |
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109 | numonyx.waitwr = 0x3; |
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110 | |
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111 | /* 16 bus turnaround cycles */ |
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112 | numonyx.waitrun = 0xf; |
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113 | #endif |
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114 | |
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115 | /* Set pin functions for EMC */ |
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116 | PINSEL5 = (PINSEL5 & 0xf000f000) | 0x05550555; |
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117 | PINSEL6 = 0x55555555; |
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118 | PINSEL8 = 0x55555555; |
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119 | PINSEL9 = (PINSEL9 & 0x0f000000) | 0x50555555; |
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120 | |
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121 | #ifdef LPC24XX_EMC_NUMONYX |
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122 | /* Static Memory 1 settings */ |
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123 | bsp_start_memcpy_arm( |
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124 | (int *) EMC_STA_BASE_1, |
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125 | (const int *) &numonyx, |
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126 | sizeof(numonyx) |
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127 | ); |
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128 | #endif |
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129 | } |
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130 | |
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131 | /** |
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132 | * @brief EMC initialization hook 1. |
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133 | */ |
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134 | static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_1(void) |
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135 | { |
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136 | /* Use normal memory map */ |
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137 | EMC_CTRL = CLEAR_FLAG(EMC_CTRL, 0x2); |
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138 | |
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139 | #ifdef LPC24XX_EMC_MICRON |
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140 | /* Check if we need to initialize it */ |
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141 | if (IS_FLAG_CLEARED(EMC_DYN_CFG0, 0x00080000)) { |
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142 | /* |
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143 | * The buffer enable bit is not set. Now we assume that the controller |
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144 | * is not properly initialized. |
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145 | */ |
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146 | |
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147 | /* Global dynamic settings */ |
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148 | |
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149 | /* FIXME */ |
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150 | EMC_DYN_APR = 2; |
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151 | |
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152 | /* Data-in to active command period tWR + tRP */ |
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153 | EMC_DYN_DAL = 4; |
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154 | |
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155 | /* Load mode register to active or refresh command period 2 tCK */ |
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156 | EMC_DYN_MRD = 1; |
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157 | |
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158 | /* Active to precharge command period 44 ns */ |
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159 | EMC_DYN_RAS = 3; |
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160 | |
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161 | /* Active to active command period 66 ns */ |
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162 | EMC_DYN_RC = 4; |
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163 | |
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164 | /* Use command delayed strategy */ |
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165 | EMC_DYN_RD_CFG = 1; |
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166 | |
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167 | /* Auto refresh period 66 ns */ |
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168 | EMC_DYN_RFC = 4; |
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169 | |
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170 | /* Precharge command period 20 ns */ |
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171 | EMC_DYN_RP = 1; |
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172 | |
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173 | /* Active bank a to active bank b command period 15 ns */ |
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174 | EMC_DYN_RRD = 1; |
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175 | |
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176 | /* FIXME */ |
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177 | EMC_DYN_SREX = 5; |
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178 | |
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179 | /* Write recovery time 15 ns */ |
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180 | EMC_DYN_WR = 1; |
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181 | |
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182 | /* Exit self refresh to active command period 75 ns */ |
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183 | EMC_DYN_XSR = 5; |
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184 | |
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185 | /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */ |
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186 | |
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187 | /* |
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188 | * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes |
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189 | */ |
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190 | EMC_DYN_CFG0 = 0x0280; |
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191 | |
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192 | /* CAS and RAS latency */ |
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193 | EMC_DYN_RASCAS0 = 0x0202; |
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194 | |
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195 | /* Wait 50 micro seconds */ |
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196 | lpc24xx_cpu_delay(3600); |
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197 | |
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198 | /* Send command: NOP */ |
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199 | EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_NOP; |
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200 | |
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201 | /* Wait 50 micro seconds */ |
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202 | lpc24xx_cpu_delay(3600); |
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203 | |
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204 | /* Send command: PRECHARGE ALL */ |
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205 | EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_PALL; |
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206 | |
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207 | /* Shortest possible refresh period */ |
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208 | EMC_DYN_RFSH = 0x01; |
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209 | |
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210 | /* Wait at least 128 AHB clock cycles */ |
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211 | lpc24xx_cpu_delay(128); |
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212 | |
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213 | /* Wait 1 micro second */ |
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214 | lpc24xx_cpu_delay(72); |
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215 | |
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216 | /* Set refresh period */ |
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217 | EMC_DYN_RFSH = 0x46; |
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218 | |
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219 | /* Send command: MODE */ |
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220 | EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_MODE; |
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221 | |
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222 | /* Set mode register in SDRAM */ |
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223 | *((volatile uint32_t *) (0xa0000000 | (0x23 << (1 + 2 + 8)))); |
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224 | |
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225 | /* Send command: NORMAL */ |
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226 | EMC_DYN_CTRL = 0; |
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227 | |
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228 | /* Enable buffer */ |
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229 | EMC_DYN_CFG0 |= 0x00080000; |
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230 | |
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231 | /* Test RAM */ |
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232 | lpc24xx_ram_test_32(); |
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233 | } |
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234 | #endif |
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235 | } |
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236 | |
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237 | static void __attribute__((section(".bsp_start"))) lpc24xx_pll_config( |
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238 | uint32_t val |
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239 | ) |
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240 | { |
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241 | PLLCON = val; |
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242 | PLLFEED = 0xaa; |
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243 | PLLFEED = 0x55; |
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244 | } |
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245 | |
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246 | /** |
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247 | * @brief Sets the Phase Locked Loop (PLL). |
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248 | * |
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249 | * All parameter values are the actual register field values. |
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250 | * |
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251 | * @param clksrc Selects the clock source for the PLL. |
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252 | * |
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253 | * @param nsel Selects PLL pre-divider value (sometimes named psel). |
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254 | * |
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255 | * @param msel Selects PLL multiplier value. |
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256 | * |
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257 | * @param cclksel Selects the divide value for creating the CPU clock (CCLK) |
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258 | * from the PLL output. |
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259 | */ |
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260 | static void __attribute__((section(".bsp_start"))) lpc24xx_set_pll( |
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261 | unsigned clksrc, |
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262 | unsigned nsel, |
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263 | unsigned msel, |
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264 | unsigned cclksel |
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265 | ) |
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266 | { |
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267 | uint32_t pllstat = PLLSTAT; |
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268 | uint32_t pllcfg = SET_PLLCFG_NSEL(0, nsel) | SET_PLLCFG_MSEL(0, msel); |
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269 | uint32_t clksrcsel = SET_CLKSRCSEL_CLKSRC(0, clksrc); |
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270 | uint32_t cclkcfg = SET_CCLKCFG_CCLKSEL(0, cclksel | 1); |
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271 | bool pll_enabled = IS_FLAG_SET(pllstat, PLLSTAT_PLLE); |
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272 | |
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273 | /* Disconnect PLL if necessary */ |
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274 | if (IS_FLAG_SET(pllstat, PLLSTAT_PLLC)) { |
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275 | if (pll_enabled) { |
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276 | /* Check if we run already with the desired settings */ |
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277 | if (PLLCFG == pllcfg && CLKSRCSEL == clksrcsel && CCLKCFG == cclkcfg) { |
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278 | /* Nothing to do */ |
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279 | return; |
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280 | } |
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281 | lpc24xx_pll_config(PLLCON_PLLE); |
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282 | } else { |
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283 | lpc24xx_pll_config(0); |
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284 | } |
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285 | } |
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286 | |
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287 | /* Set CPU clock divider to a reasonable save value */ |
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288 | CCLKCFG = 0; |
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289 | |
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290 | /* Disable PLL if necessary */ |
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291 | if (pll_enabled) { |
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292 | lpc24xx_pll_config(0); |
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293 | } |
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294 | |
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295 | /* Select clock source */ |
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296 | CLKSRCSEL = clksrcsel; |
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297 | |
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298 | /* Set PLL Configuration Register */ |
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299 | PLLCFG = pllcfg; |
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300 | |
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301 | /* Enable PLL */ |
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302 | lpc24xx_pll_config(PLLCON_PLLE); |
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303 | |
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304 | /* Wait for lock */ |
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305 | while (IS_FLAG_CLEARED(PLLSTAT, PLLSTAT_PLOCK)) { |
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306 | /* Wait */ |
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307 | } |
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308 | |
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309 | /* Set CPU clock divider and ensure that we have an odd value */ |
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310 | CCLKCFG = cclkcfg; |
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311 | |
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312 | /* Connect PLL */ |
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313 | lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC); |
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314 | } |
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315 | |
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316 | static void __attribute__((section(".bsp_start"))) lpc24xx_init_pll(void) |
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317 | { |
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318 | /* Enable main oscillator */ |
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319 | if (IS_FLAG_CLEARED(SCS, 0x40)) { |
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320 | SCS = SET_FLAG(SCS, 0x20); |
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321 | while (IS_FLAG_CLEARED(SCS, 0x40)) { |
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322 | /* Wait */ |
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323 | } |
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324 | } |
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325 | |
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326 | /* Set PLL */ |
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327 | lpc24xx_set_pll(1, 0, 11, 3); |
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328 | } |
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329 | |
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330 | static void __attribute__((section(".bsp_start"))) lpc24xx_clear_bss(void) |
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331 | { |
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332 | const int *end = (const int *) bsp_section_bss_end; |
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333 | int *out = (int *) bsp_section_bss_begin; |
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334 | |
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335 | /* Clear BSS */ |
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336 | while (out != end) { |
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337 | *out = 0; |
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338 | ++out; |
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339 | } |
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340 | } |
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341 | |
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342 | void __attribute__((section(".bsp_start"))) bsp_start_hook_0(void) |
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343 | { |
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344 | /* Initialize PLL */ |
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345 | lpc24xx_init_pll(); |
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346 | |
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347 | /* Initialize EMC hook 0 */ |
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348 | lpc24xx_init_emc_0(); |
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349 | } |
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350 | |
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351 | void __attribute__((section(".bsp_start"))) bsp_start_hook_1(void) |
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352 | { |
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353 | /* Re-map interrupt vectors to internal RAM */ |
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354 | MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2); |
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355 | |
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356 | /* Set memory accelerator module (MAM) */ |
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357 | MAMCR = 0; |
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358 | MAMTIM = 4; |
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359 | |
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360 | /* Enable fast IO for ports 0 and 1 */ |
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361 | SCS = SET_FLAG(SCS, 0x1); |
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362 | |
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363 | /* Set fast IO */ |
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364 | FIO0DIR = 0; |
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365 | FIO1DIR = 0; |
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366 | FIO2DIR = 0; |
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367 | FIO3DIR = 0; |
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368 | FIO4DIR = 0; |
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369 | FIO0CLR = 0xffffffff; |
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370 | FIO1CLR = 0xffffffff; |
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371 | FIO2CLR = 0xffffffff; |
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372 | FIO3CLR = 0xffffffff; |
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373 | FIO4CLR = 0xffffffff; |
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374 | |
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375 | /* Initialize EMC hook 1 */ |
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376 | lpc24xx_init_emc_1(); |
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377 | |
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378 | /* Copy .text section */ |
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379 | bsp_start_memcpy_arm( |
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380 | (int *) bsp_section_text_begin, |
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381 | (const int *) bsp_section_text_load_begin, |
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382 | (size_t) bsp_section_text_size |
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383 | ); |
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384 | |
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385 | /* Copy .rodata section */ |
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386 | bsp_start_memcpy_arm( |
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387 | (int *) bsp_section_rodata_begin, |
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388 | (const int *) bsp_section_rodata_load_begin, |
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389 | (size_t) bsp_section_rodata_size |
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390 | ); |
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391 | |
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392 | /* Copy .data section */ |
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393 | bsp_start_memcpy_arm( |
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394 | (int *) bsp_section_data_begin, |
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395 | (const int *) bsp_section_data_load_begin, |
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396 | (size_t) bsp_section_data_size |
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397 | ); |
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398 | |
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399 | /* Copy .fast section */ |
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400 | bsp_start_memcpy_arm( |
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401 | (int *) bsp_section_fast_begin, |
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402 | (const int *) bsp_section_fast_load_begin, |
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403 | (size_t) bsp_section_fast_size |
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404 | ); |
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405 | |
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406 | /* Clear .bss section */ |
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407 | lpc24xx_clear_bss(); |
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408 | |
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409 | /* At this point we can use objects outside the .start section */ |
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410 | } |
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