[687e34b] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc24xx |
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| 5 | * |
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| 6 | * @brief Startup code. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[14ee5a1e] | 10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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[d74ed4a] | 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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[687e34b] | 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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[14ee5a1e] | 23 | #include <bsp.h> |
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[4a6cc2a] | 24 | #include <bsp/io.h> |
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[687e34b] | 25 | #include <bsp/start.h> |
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[d74ed4a] | 26 | #include <bsp/lpc24xx.h> |
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| 27 | #include <bsp/lpc-emc.h> |
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[4f609eec] | 28 | #include <bsp/start-config.h> |
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[687e34b] | 29 | |
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[4a6cc2a] | 30 | static BSP_START_TEXT_SECTION void lpc24xx_cpu_delay(unsigned ticks) |
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[4f609eec] | 31 | { |
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| 32 | unsigned i = 0; |
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[687e34b] | 33 | |
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[4f609eec] | 34 | /* One loop execution needs four instructions */ |
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| 35 | ticks /= 4; |
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[687e34b] | 36 | |
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[4f609eec] | 37 | for (i = 0; i <= ticks; ++i) { |
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| 38 | __asm__ volatile ("nop"); |
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[687e34b] | 39 | } |
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[4f609eec] | 40 | } |
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[d74ed4a] | 41 | |
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[4a6cc2a] | 42 | static BSP_START_TEXT_SECTION void lpc24xx_udelay(unsigned us) |
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[4f609eec] | 43 | { |
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| 44 | lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000)); |
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| 45 | } |
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[687e34b] | 46 | |
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[4a6cc2a] | 47 | static BSP_START_TEXT_SECTION void lpc24xx_init_pinsel(void) |
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[d74ed4a] | 48 | { |
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[4a6cc2a] | 49 | lpc24xx_pin_config( |
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| 50 | &lpc24xx_start_config_pinsel [0], |
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| 51 | LPC24XX_PIN_SET_FUNCTION |
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[4f609eec] | 52 | ); |
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[d74ed4a] | 53 | } |
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| 54 | |
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[4a6cc2a] | 55 | static BSP_START_TEXT_SECTION void lpc24xx_init_emc_static(void) |
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[687e34b] | 56 | { |
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[4f609eec] | 57 | size_t i = 0; |
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| 58 | size_t chip_count = lpc24xx_start_config_emc_static_chip_count; |
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[687e34b] | 59 | |
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[4f609eec] | 60 | for (i = 0; i < chip_count; ++i) { |
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| 61 | const lpc24xx_emc_static_chip_config *chip_config = |
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| 62 | &lpc24xx_start_config_emc_static_chip [i]; |
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[d74ed4a] | 63 | lpc24xx_emc_static_chip_config chip_config_on_stack; |
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[4f609eec] | 64 | size_t config_size = sizeof(chip_config_on_stack.config); |
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[687e34b] | 65 | |
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[d74ed4a] | 66 | bsp_start_memcpy( |
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[4f609eec] | 67 | (int *) &chip_config_on_stack.config, |
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| 68 | (const int *) &chip_config->config, |
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| 69 | config_size |
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[d74ed4a] | 70 | ); |
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[22f107b6] | 71 | bsp_start_memcpy( |
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[4f609eec] | 72 | (int *) chip_config->chip_select, |
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| 73 | (const int *) &chip_config_on_stack.config, |
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| 74 | config_size |
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[687e34b] | 75 | ); |
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[4f609eec] | 76 | } |
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[687e34b] | 77 | } |
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| 78 | |
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[4a6cc2a] | 79 | static BSP_START_TEXT_SECTION void lpc24xx_init_emc_dynamic(void) |
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[d74ed4a] | 80 | { |
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[4f609eec] | 81 | size_t chip_count = lpc24xx_start_config_emc_dynamic_chip_count; |
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[32b8506] | 82 | |
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[4f609eec] | 83 | if (chip_count > 0) { |
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| 84 | bool do_initialization = true; |
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| 85 | size_t i = 0; |
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[32b8506] | 86 | |
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[4f609eec] | 87 | for (i = 0; do_initialization && i < chip_count; ++i) { |
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| 88 | const lpc24xx_emc_dynamic_chip_config *chip_cfg = |
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| 89 | &lpc24xx_start_config_emc_dynamic_chip [i]; |
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| 90 | volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select; |
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[32b8506] | 91 | |
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[4f609eec] | 92 | do_initialization = (chip_select->config & EMC_DYN_CFG_B) == 0; |
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| 93 | } |
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[32b8506] | 94 | |
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[4f609eec] | 95 | if (do_initialization) { |
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| 96 | volatile lpc_emc *emc = (volatile lpc_emc *) EMC_BASE_ADDR; |
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| 97 | const lpc24xx_emc_dynamic_config *cfg = |
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| 98 | &lpc24xx_start_config_emc_dynamic [0]; |
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| 99 | uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS; |
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| 100 | |
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[14ee5a1e] | 101 | #ifdef ARM_MULTILIB_ARCH_V7M |
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| 102 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 103 | |
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| 104 | /* Delay control */ |
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| 105 | scb->emcdlyctl = cfg->emcdlyctl; |
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| 106 | #endif |
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| 107 | |
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[4f609eec] | 108 | emc->dynamicreadconfig = cfg->readconfig; |
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| 109 | |
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| 110 | /* Timings */ |
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| 111 | emc->dynamictrp = cfg->trp; |
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| 112 | emc->dynamictras = cfg->tras; |
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| 113 | emc->dynamictsrex = cfg->tsrex; |
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| 114 | emc->dynamictapr = cfg->tapr; |
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| 115 | emc->dynamictdal = cfg->tdal; |
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| 116 | emc->dynamictwr = cfg->twr; |
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| 117 | emc->dynamictrc = cfg->trc; |
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| 118 | emc->dynamictrfc = cfg->trfc; |
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| 119 | emc->dynamictxsr = cfg->txsr; |
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| 120 | emc->dynamictrrd = cfg->trrd; |
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| 121 | emc->dynamictmrd = cfg->tmrd; |
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| 122 | |
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| 123 | /* NOP period */ |
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[d74ed4a] | 124 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP; |
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| 125 | lpc24xx_udelay(200); |
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| 126 | |
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[4f609eec] | 127 | /* Precharge */ |
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[d74ed4a] | 128 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL; |
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[4f609eec] | 129 | emc->dynamicrefresh = 1; |
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[32b8506] | 130 | |
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[d74ed4a] | 131 | /* |
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| 132 | * Perform several refresh cycles with a memory refresh every 16 AHB |
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| 133 | * clock cycles. Wait until eight SDRAM refresh cycles have occurred |
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| 134 | * (128 AHB clock cycles). |
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| 135 | */ |
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[687e34b] | 136 | lpc24xx_cpu_delay(128); |
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[32b8506] | 137 | |
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[4f609eec] | 138 | /* Refresh timing */ |
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| 139 | emc->dynamicrefresh = cfg->refresh; |
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| 140 | lpc24xx_cpu_delay(128); |
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[32b8506] | 141 | |
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[4f609eec] | 142 | for (i = 0; i < chip_count; ++i) { |
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| 143 | const lpc24xx_emc_dynamic_chip_config *chip_cfg = |
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| 144 | &lpc24xx_start_config_emc_dynamic_chip [i]; |
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| 145 | volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select; |
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| 146 | uint32_t config = chip_cfg->config; |
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[32b8506] | 147 | |
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[4f609eec] | 148 | /* Chip select */ |
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| 149 | chip_select->config = config; |
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| 150 | chip_select->rascas = chip_cfg->rascas; |
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[32b8506] | 151 | |
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[4f609eec] | 152 | /* Set modes */ |
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| 153 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE; |
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| 154 | *(volatile uint32_t *)(chip_cfg->address + chip_cfg->mode); |
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[32b8506] | 155 | |
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[4f609eec] | 156 | /* Enable buffer */ |
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| 157 | chip_select->config = config | EMC_DYN_CFG_B; |
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| 158 | } |
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[32b8506] | 159 | |
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[4a6cc2a] | 160 | emc->dynamiccontrol = 0; |
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[687e34b] | 161 | } |
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[4f609eec] | 162 | } |
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[687e34b] | 163 | } |
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| 164 | |
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[4a6cc2a] | 165 | static BSP_START_TEXT_SECTION void lpc24xx_init_main_oscillator(void) |
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| 166 | { |
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| 167 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 168 | if ((SCS & 0x40) == 0) { |
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| 169 | SCS |= 0x20; |
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| 170 | while ((SCS & 0x40) == 0) { |
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| 171 | /* Wait */ |
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| 172 | } |
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| 173 | } |
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[14ee5a1e] | 174 | #else |
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| 175 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 176 | |
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| 177 | if ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) { |
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| 178 | scb->scs |= LPC17XX_SCB_SCS_OSC_ENABLE; |
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| 179 | while ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) { |
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| 180 | /* Wait */ |
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| 181 | } |
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| 182 | } |
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[4a6cc2a] | 183 | #endif |
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| 184 | } |
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| 185 | |
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| 186 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 187 | |
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| 188 | static BSP_START_TEXT_SECTION void lpc24xx_pll_config( |
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[687e34b] | 189 | uint32_t val |
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| 190 | ) |
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| 191 | { |
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| 192 | PLLCON = val; |
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| 193 | PLLFEED = 0xaa; |
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| 194 | PLLFEED = 0x55; |
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| 195 | } |
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| 196 | |
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| 197 | /** |
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| 198 | * @brief Sets the Phase Locked Loop (PLL). |
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| 199 | * |
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| 200 | * All parameter values are the actual register field values. |
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| 201 | * |
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| 202 | * @param clksrc Selects the clock source for the PLL. |
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| 203 | * |
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| 204 | * @param nsel Selects PLL pre-divider value (sometimes named psel). |
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| 205 | * |
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| 206 | * @param msel Selects PLL multiplier value. |
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| 207 | * |
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| 208 | * @param cclksel Selects the divide value for creating the CPU clock (CCLK) |
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| 209 | * from the PLL output. |
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| 210 | */ |
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[4a6cc2a] | 211 | static BSP_START_TEXT_SECTION void lpc24xx_set_pll( |
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[687e34b] | 212 | unsigned clksrc, |
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| 213 | unsigned nsel, |
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| 214 | unsigned msel, |
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| 215 | unsigned cclksel |
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| 216 | ) |
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| 217 | { |
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| 218 | uint32_t pllstat = PLLSTAT; |
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| 219 | uint32_t pllcfg = SET_PLLCFG_NSEL(0, nsel) | SET_PLLCFG_MSEL(0, msel); |
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| 220 | uint32_t clksrcsel = SET_CLKSRCSEL_CLKSRC(0, clksrc); |
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| 221 | uint32_t cclkcfg = SET_CCLKCFG_CCLKSEL(0, cclksel | 1); |
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[edf846e4] | 222 | bool pll_enabled = (pllstat & PLLSTAT_PLLE) != 0; |
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[687e34b] | 223 | |
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| 224 | /* Disconnect PLL if necessary */ |
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[edf846e4] | 225 | if ((pllstat & PLLSTAT_PLLC) != 0) { |
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[687e34b] | 226 | if (pll_enabled) { |
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| 227 | /* Check if we run already with the desired settings */ |
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| 228 | if (PLLCFG == pllcfg && CLKSRCSEL == clksrcsel && CCLKCFG == cclkcfg) { |
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| 229 | /* Nothing to do */ |
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| 230 | return; |
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| 231 | } |
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| 232 | lpc24xx_pll_config(PLLCON_PLLE); |
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| 233 | } else { |
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| 234 | lpc24xx_pll_config(0); |
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| 235 | } |
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| 236 | } |
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| 237 | |
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| 238 | /* Set CPU clock divider to a reasonable save value */ |
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| 239 | CCLKCFG = 0; |
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| 240 | |
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| 241 | /* Disable PLL if necessary */ |
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| 242 | if (pll_enabled) { |
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| 243 | lpc24xx_pll_config(0); |
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| 244 | } |
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| 245 | |
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| 246 | /* Select clock source */ |
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| 247 | CLKSRCSEL = clksrcsel; |
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| 248 | |
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| 249 | /* Set PLL Configuration Register */ |
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| 250 | PLLCFG = pllcfg; |
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| 251 | |
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| 252 | /* Enable PLL */ |
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| 253 | lpc24xx_pll_config(PLLCON_PLLE); |
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| 254 | |
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| 255 | /* Wait for lock */ |
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[edf846e4] | 256 | while ((PLLSTAT & PLLSTAT_PLOCK) == 0) { |
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[687e34b] | 257 | /* Wait */ |
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| 258 | } |
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| 259 | |
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| 260 | /* Set CPU clock divider and ensure that we have an odd value */ |
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| 261 | CCLKCFG = cclkcfg; |
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| 262 | |
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| 263 | /* Connect PLL */ |
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| 264 | lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC); |
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| 265 | } |
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| 266 | |
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[14ee5a1e] | 267 | #else /* ARM_MULTILIB_ARCH_V4 */ |
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| 268 | |
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| 269 | static BSP_START_TEXT_SECTION void lpc17xx_pll_config( |
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| 270 | volatile lpc17xx_pll *pll, |
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| 271 | uint32_t val |
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| 272 | ) |
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| 273 | { |
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| 274 | pll->con = val; |
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| 275 | pll->feed = 0xaa; |
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| 276 | pll->feed = 0x55; |
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| 277 | } |
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| 278 | |
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| 279 | static BSP_START_TEXT_SECTION void lpc17xx_set_pll( |
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| 280 | unsigned msel, |
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| 281 | unsigned psel, |
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| 282 | unsigned cclkdiv |
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| 283 | ) |
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| 284 | { |
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| 285 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 286 | volatile lpc17xx_pll *pll = &scb->pll_0; |
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| 287 | uint32_t pllcfg = LPC17XX_PLL_SEL_MSEL(msel) |
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| 288 | | LPC17XX_PLL_SEL_PSEL(psel); |
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| 289 | uint32_t pllstat = LPC17XX_PLL_STAT_PLLE |
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| 290 | | LPC17XX_PLL_STAT_PLOCK | pllcfg; |
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| 291 | uint32_t cclksel_cclkdiv = LPC17XX_SCB_CCLKSEL_CCLKDIV(cclkdiv); |
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| 292 | uint32_t cclksel = LPC17XX_SCB_CCLKSEL_CCLKSEL | cclksel_cclkdiv; |
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| 293 | |
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| 294 | if ( |
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| 295 | pll->stat != pllstat |
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| 296 | || scb->cclksel != cclksel |
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| 297 | || scb->clksrcsel != LPC17XX_SCB_CLKSRCSEL_CLKSRC |
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| 298 | ) { |
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| 299 | /* Use SYSCLK for CCLK */ |
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| 300 | scb->cclksel = LPC17XX_SCB_CCLKSEL_CCLKDIV(1); |
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| 301 | |
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| 302 | /* Turn off USB */ |
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| 303 | scb->usbclksel = 0; |
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| 304 | |
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| 305 | /* Disable PLL */ |
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| 306 | lpc17xx_pll_config(pll, 0); |
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| 307 | |
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| 308 | /* Select main oscillator as clock source */ |
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| 309 | scb->clksrcsel = LPC17XX_SCB_CLKSRCSEL_CLKSRC; |
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| 310 | |
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| 311 | /* Set PLL configuration */ |
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| 312 | pll->cfg = pllcfg; |
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| 313 | |
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| 314 | /* Set the CCLK, PCLK and EMCCLK divider */ |
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| 315 | scb->cclksel = cclksel_cclkdiv; |
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[f72b2de] | 316 | scb->pclksel = LPC17XX_SCB_PCLKSEL_PCLKDIV(cclkdiv * LPC24XX_PCLKDIV); |
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[14ee5a1e] | 317 | scb->emcclksel = LPC24XX_EMCCLKDIV == 1 ? 0 : LPC17XX_SCB_EMCCLKSEL_EMCDIV; |
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| 318 | |
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| 319 | /* Enable PLL */ |
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| 320 | lpc17xx_pll_config(pll, LPC17XX_PLL_CON_PLLE); |
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| 321 | |
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| 322 | /* Wait for lock */ |
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| 323 | while ((pll->stat & LPC17XX_PLL_STAT_PLOCK) == 0) { |
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| 324 | /* Wait */ |
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| 325 | } |
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| 326 | |
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| 327 | /* Use the PLL clock */ |
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| 328 | scb->cclksel = cclksel; |
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| 329 | } |
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| 330 | } |
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| 331 | |
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[4a6cc2a] | 332 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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[687e34b] | 333 | |
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[4a6cc2a] | 334 | static BSP_START_TEXT_SECTION void lpc24xx_init_pll(void) |
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| 335 | { |
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| 336 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 337 | #if LPC24XX_OSCILLATOR_MAIN == 12000000U |
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| 338 | #if LPC24XX_CCLK == 72000000U |
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| 339 | lpc24xx_set_pll(1, 0, 11, 3); |
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| 340 | #elif LPC24XX_CCLK == 51612800U |
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| 341 | lpc24xx_set_pll(1, 30, 399, 5); |
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| 342 | #else |
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| 343 | #error "unexpected CCLK" |
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| 344 | #endif |
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| 345 | #elif LPC24XX_OSCILLATOR_MAIN == 3686400U |
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| 346 | #if LPC24XX_CCLK == 58982400U |
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| 347 | lpc24xx_set_pll(1, 0, 47, 5); |
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| 348 | #else |
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| 349 | #error "unexpected CCLK" |
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| 350 | #endif |
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[4f609eec] | 351 | #else |
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[4a6cc2a] | 352 | #error "unexpected main oscillator frequency" |
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[4f609eec] | 353 | #endif |
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[14ee5a1e] | 354 | #else |
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| 355 | #if LPC24XX_OSCILLATOR_MAIN == 12000000U |
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| 356 | #if LPC24XX_CCLK == 120000000U |
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| 357 | lpc17xx_set_pll(9, 0, 1); |
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| 358 | #elif LPC24XX_CCLK == 96000000U |
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| 359 | lpc17xx_set_pll(7, 0, 1); |
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| 360 | #elif LPC24XX_CCLK == 72000000U |
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| 361 | lpc17xx_set_pll(5, 1, 1); |
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| 362 | #elif LPC24XX_CCLK == 48000000U |
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| 363 | lpc17xx_set_pll(3, 1, 1); |
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| 364 | #else |
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| 365 | #error "unexpected CCLK" |
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| 366 | #endif |
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| 367 | #else |
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| 368 | #error "unexpected main oscillator frequency" |
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| 369 | #endif |
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[22f107b6] | 370 | #endif |
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[687e34b] | 371 | } |
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| 372 | |
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[4a6cc2a] | 373 | static BSP_START_TEXT_SECTION void lpc24xx_init_memory_map(void) |
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[687e34b] | 374 | { |
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[4a6cc2a] | 375 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 376 | /* Re-map interrupt vectors to internal RAM */ |
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| 377 | MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2); |
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[14ee5a1e] | 378 | #else |
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| 379 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 380 | |
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| 381 | scb->memmap = LPC17XX_SCB_MEMMAP_MAP; |
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[4a6cc2a] | 382 | #endif |
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[687e34b] | 383 | |
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[4a6cc2a] | 384 | /* Use normal memory map */ |
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| 385 | EMC_CTRL &= ~0x2U; |
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[687e34b] | 386 | } |
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| 387 | |
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[4a6cc2a] | 388 | static BSP_START_TEXT_SECTION void lpc24xx_init_memory_accelerator(void) |
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[687e34b] | 389 | { |
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[4a6cc2a] | 390 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 391 | /* Fully enable memory accelerator module functions (MAM) */ |
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| 392 | MAMCR = 0; |
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| 393 | #if LPC24XX_CCLK <= 20000000U |
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| 394 | MAMTIM = 0x1; |
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| 395 | #elif LPC24XX_CCLK <= 40000000U |
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| 396 | MAMTIM = 0x2; |
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| 397 | #elif LPC24XX_CCLK <= 60000000U |
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| 398 | MAMTIM = 0x3; |
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| 399 | #else |
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| 400 | MAMTIM = 0x4; |
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| 401 | #endif |
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| 402 | MAMCR = 0x2; |
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[687e34b] | 403 | |
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[4a6cc2a] | 404 | /* Enable fast IO for ports 0 and 1 */ |
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| 405 | SCS |= 0x1; |
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[14ee5a1e] | 406 | #else |
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| 407 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 408 | |
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| 409 | #if LPC24XX_CCLK <= 20000000U |
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| 410 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x0); |
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| 411 | #elif LPC24XX_CCLK <= 40000000U |
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| 412 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x1); |
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| 413 | #elif LPC24XX_CCLK <= 60000000U |
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| 414 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x2); |
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| 415 | #elif LPC24XX_CCLK <= 80000000U |
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| 416 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x3); |
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| 417 | #elif LPC24XX_CCLK <= 100000000U |
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| 418 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x4); |
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| 419 | #else |
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| 420 | scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x5); |
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| 421 | #endif |
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[22f107b6] | 422 | #endif |
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[4a6cc2a] | 423 | } |
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[687e34b] | 424 | |
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[4a6cc2a] | 425 | static BSP_START_TEXT_SECTION void lpc24xx_stop_gpdma(void) |
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| 426 | { |
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[22f107b6] | 427 | #ifdef LPC24XX_STOP_GPDMA |
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[4a6cc2a] | 428 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 429 | bool has_power = (PCONP & PCONP_GPDMA) != 0; |
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[14ee5a1e] | 430 | #else |
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| 431 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 432 | bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_GPDMA) != 0; |
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[4a6cc2a] | 433 | #endif |
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| 434 | |
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| 435 | if (has_power) { |
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[22f107b6] | 436 | GPDMA_CONFIG = 0; |
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[4a6cc2a] | 437 | |
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| 438 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 439 | PCONP &= ~PCONP_GPDMA; |
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[14ee5a1e] | 440 | #else |
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| 441 | scb->pconp &= ~LPC17XX_SCB_PCONP_GPDMA; |
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[4a6cc2a] | 442 | #endif |
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[22f107b6] | 443 | } |
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| 444 | #endif |
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[4a6cc2a] | 445 | } |
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[22f107b6] | 446 | |
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[4a6cc2a] | 447 | static BSP_START_TEXT_SECTION void lpc24xx_stop_ethernet(void) |
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| 448 | { |
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[22f107b6] | 449 | #ifdef LPC24XX_STOP_ETHERNET |
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[4a6cc2a] | 450 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 451 | bool has_power = (PCONP & PCONP_ETHERNET) != 0; |
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[14ee5a1e] | 452 | #else |
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| 453 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 454 | bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_ENET) != 0; |
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[4a6cc2a] | 455 | #endif |
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| 456 | |
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| 457 | if (has_power) { |
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[22f107b6] | 458 | MAC_COMMAND = 0x38; |
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| 459 | MAC_MAC1 = 0xcf00; |
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| 460 | MAC_MAC1 = 0; |
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[4a6cc2a] | 461 | |
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| 462 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 463 | PCONP &= ~PCONP_ETHERNET; |
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[14ee5a1e] | 464 | #else |
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| 465 | scb->pconp &= ~LPC17XX_SCB_PCONP_ENET; |
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[4a6cc2a] | 466 | #endif |
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[22f107b6] | 467 | } |
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| 468 | #endif |
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[4a6cc2a] | 469 | } |
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[22f107b6] | 470 | |
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[4a6cc2a] | 471 | static BSP_START_TEXT_SECTION void lpc24xx_stop_usb(void) |
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| 472 | { |
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[22f107b6] | 473 | #ifdef LPC24XX_STOP_USB |
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[4a6cc2a] | 474 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 475 | bool has_power = (PCONP & PCONP_USB) != 0; |
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[14ee5a1e] | 476 | #else |
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| 477 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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| 478 | bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_USB) != 0; |
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[4a6cc2a] | 479 | #endif |
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| 480 | |
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| 481 | if (has_power) { |
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[22f107b6] | 482 | OTG_CLK_CTRL = 0; |
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[4a6cc2a] | 483 | |
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| 484 | #ifdef ARM_MULTILIB_ARCH_V4 |
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| 485 | PCONP &= ~PCONP_USB; |
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[14ee5a1e] | 486 | #else |
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| 487 | scb->pconp &= ~LPC17XX_SCB_PCONP_USB; |
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| 488 | scb->usbclksel = 0; |
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[4a6cc2a] | 489 | #endif |
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[22f107b6] | 490 | } |
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| 491 | #endif |
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[4a6cc2a] | 492 | } |
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[22f107b6] | 493 | |
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[14ee5a1e] | 494 | static BSP_START_TEXT_SECTION void lpc24xx_init_mpu(void) |
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| 495 | { |
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| 496 | #ifdef ARM_MULTILIB_ARCH_V7M |
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| 497 | volatile ARMV7M_MPU *mpu = _ARMV7M_MPU; |
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[a94bcc5a] | 498 | size_t region_count = lpc24xx_start_config_mpu_region_count; |
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[14ee5a1e] | 499 | size_t i = 0; |
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| 500 | |
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[a94bcc5a] | 501 | for (i = 0; i < region_count; ++i) { |
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| 502 | mpu->rbar = lpc24xx_start_config_mpu_region [i].rbar; |
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| 503 | mpu->rasr = lpc24xx_start_config_mpu_region [i].rasr; |
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[14ee5a1e] | 504 | } |
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| 505 | |
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[a94bcc5a] | 506 | if (region_count > 0) { |
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[14ee5a1e] | 507 | mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE; |
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| 508 | } |
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| 509 | #endif |
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| 510 | } |
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| 511 | |
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[4a6cc2a] | 512 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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| 513 | { |
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| 514 | lpc24xx_init_main_oscillator(); |
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| 515 | lpc24xx_init_pll(); |
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| 516 | lpc24xx_init_pinsel(); |
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| 517 | lpc24xx_init_emc_static(); |
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| 518 | } |
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[687e34b] | 519 | |
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[4a6cc2a] | 520 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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| 521 | { |
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| 522 | lpc24xx_init_memory_map(); |
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| 523 | lpc24xx_init_memory_accelerator(); |
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| 524 | lpc24xx_init_emc_dynamic(); |
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[14ee5a1e] | 525 | lpc24xx_init_mpu(); |
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[4a6cc2a] | 526 | lpc24xx_stop_gpdma(); |
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| 527 | lpc24xx_stop_ethernet(); |
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| 528 | lpc24xx_stop_usb(); |
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| 529 | bsp_start_copy_sections(); |
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[fb0584f] | 530 | bsp_start_clear_bss(); |
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[687e34b] | 531 | |
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| 532 | /* At this point we can use objects outside the .start section */ |
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| 533 | } |
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