1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx_libi2c |
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5 | * |
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6 | * @brief LibI2C bus driver for the Synchronous Serial Port (SSP). |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be found in the file |
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18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <stdbool.h> |
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22 | |
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23 | #include <bsp/ssp.h> |
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24 | #include <bsp/lpc24xx.h> |
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25 | #include <bsp/irq.h> |
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26 | #include <bsp/system-clocks.h> |
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27 | #include <bsp/dma.h> |
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28 | |
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29 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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30 | |
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31 | #include <rtems/status-checks.h> |
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32 | |
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33 | #define LPC24XX_SSP_NUMBER 2 |
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34 | |
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35 | #define LPC24XX_SSP_FIFO_SIZE 8 |
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36 | |
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37 | #define LPC24XX_SSP_BAUD_RATE 2000000 |
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38 | |
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39 | typedef enum { |
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40 | LPC24XX_SSP_DMA_INVALID = 0, |
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41 | LPC24XX_SSP_DMA_AVAILABLE = 1, |
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42 | LPC24XX_SSP_DMA_NOT_INITIALIZED = 2, |
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43 | LPC24XX_SSP_DMA_INITIALIZATION = 3, |
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44 | LPC24XX_SSP_DMA_TRANSFER_FLAG = 0x80000000U, |
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45 | LPC24XX_SSP_DMA_WAIT = 1 | LPC24XX_SSP_DMA_TRANSFER_FLAG, |
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46 | LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0 = 2 | LPC24XX_SSP_DMA_TRANSFER_FLAG, |
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47 | LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1 = 3 | LPC24XX_SSP_DMA_TRANSFER_FLAG, |
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48 | LPC24XX_SSP_DMA_ERROR = 4 | LPC24XX_SSP_DMA_TRANSFER_FLAG, |
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49 | LPC24XX_SSP_DMA_DONE = 5 | LPC24XX_SSP_DMA_TRANSFER_FLAG |
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50 | } lpc24xx_ssp_dma_status; |
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51 | |
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52 | typedef struct { |
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53 | rtems_libi2c_bus_t bus; |
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54 | volatile lpc24xx_ssp *regs; |
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55 | unsigned clock; |
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56 | uint32_t idle_char; |
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57 | } lpc24xx_ssp_bus_entry; |
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58 | |
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59 | typedef struct { |
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60 | lpc24xx_ssp_dma_status status; |
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61 | lpc24xx_ssp_bus_entry *bus; |
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62 | rtems_libi2c_read_write_done_t done; |
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63 | int n; |
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64 | void *arg; |
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65 | } lpc24xx_ssp_dma_entry; |
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66 | |
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67 | static lpc24xx_ssp_dma_entry lpc24xx_ssp_dma_data = { |
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68 | .status = LPC24XX_SSP_DMA_NOT_INITIALIZED, |
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69 | .bus = NULL, |
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70 | .done = NULL, |
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71 | .n = 0, |
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72 | .arg = NULL |
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73 | }; |
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74 | |
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75 | static uint32_t lpc24xx_ssp_trash = 0; |
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76 | |
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77 | static inline bool lpc24xx_ssp_is_busy(const lpc24xx_ssp_bus_entry *bus) |
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78 | { |
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79 | return lpc24xx_ssp_dma_data.bus == bus |
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80 | && lpc24xx_ssp_dma_data.status != LPC24XX_SSP_DMA_AVAILABLE; |
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81 | } |
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82 | |
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83 | static void lpc24xx_ssp_handler(void *arg) |
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84 | { |
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85 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) arg; |
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86 | volatile lpc24xx_ssp *regs = e->regs; |
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87 | uint32_t mis = regs->mis; |
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88 | uint32_t icr = 0; |
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89 | |
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90 | if (IS_FLAG_SET(mis, SSP_MIS_RORRIS)) { |
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91 | /* TODO */ |
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92 | printk("%s: Receiver overrun!\n", __func__); |
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93 | icr |= SSP_ICR_RORRIS; |
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94 | } |
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95 | |
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96 | regs->icr = icr; |
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97 | } |
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98 | |
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99 | static void lpc24xx_ssp_dma_handler(void *arg) |
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100 | { |
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101 | lpc24xx_ssp_dma_entry *e = (lpc24xx_ssp_dma_entry *) arg; |
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102 | lpc24xx_ssp_dma_status status = e->status; |
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103 | uint32_t tc = 0; |
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104 | uint32_t err = 0; |
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105 | int rv = 0; |
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106 | |
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107 | /* Return if we are not in a transfer status */ |
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108 | if (IS_FLAG_CLEARED(status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) { |
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109 | return; |
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110 | } |
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111 | |
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112 | /* Get interrupt status */ |
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113 | tc = GPDMA_INT_TCSTAT; |
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114 | err = GPDMA_INT_ERR_STAT; |
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115 | |
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116 | /* Clear interrupt status */ |
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117 | GPDMA_INT_TCCLR = tc; |
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118 | GPDMA_INT_ERR_CLR = err; |
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119 | |
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120 | /* Change status */ |
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121 | if (err == 0) { |
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122 | switch (status) { |
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123 | case LPC24XX_SSP_DMA_WAIT: |
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124 | if (ARE_FLAGS_SET(tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) { |
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125 | status = LPC24XX_SSP_DMA_DONE; |
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126 | } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) { |
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127 | status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1; |
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128 | } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) { |
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129 | status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0; |
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130 | } |
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131 | break; |
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132 | case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0: |
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133 | if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) { |
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134 | status = LPC24XX_SSP_DMA_ERROR; |
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135 | } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) { |
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136 | status = LPC24XX_SSP_DMA_DONE; |
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137 | } |
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138 | break; |
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139 | case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1: |
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140 | if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) { |
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141 | status = LPC24XX_SSP_DMA_ERROR; |
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142 | } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) { |
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143 | status = LPC24XX_SSP_DMA_DONE; |
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144 | } |
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145 | break; |
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146 | default: |
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147 | status = LPC24XX_SSP_DMA_ERROR; |
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148 | break; |
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149 | } |
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150 | } else { |
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151 | status = LPC24XX_SSP_DMA_ERROR; |
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152 | } |
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153 | |
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154 | /* Error cleanup */ |
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155 | if (status == LPC24XX_SSP_DMA_ERROR) { |
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156 | lpc24xx_dma_channel_disable(0, true); |
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157 | lpc24xx_dma_channel_disable(1, true); |
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158 | status = LPC24XX_SSP_DMA_DONE; |
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159 | rv = -RTEMS_IO_ERROR; |
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160 | } |
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161 | |
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162 | /* Done */ |
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163 | if (status == LPC24XX_SSP_DMA_DONE) { |
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164 | status = LPC24XX_SSP_DMA_AVAILABLE; |
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165 | if (e->done != NULL) { |
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166 | e->done(rv, e->n, e->arg); |
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167 | e->done = NULL; |
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168 | } |
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169 | } |
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170 | |
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171 | /* Set status */ |
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172 | e->status = status; |
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173 | } |
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174 | |
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175 | static rtems_status_code lpc24xx_ssp_init(rtems_libi2c_bus_t *bus) |
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176 | { |
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177 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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178 | rtems_interrupt_level level; |
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179 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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180 | volatile lpc24xx_ssp *regs = e->regs; |
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181 | unsigned pclk = lpc24xx_cclk(); |
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182 | unsigned pre = |
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183 | ((pclk + LPC24XX_SSP_BAUD_RATE - 1) / LPC24XX_SSP_BAUD_RATE + 1) & ~1U; |
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184 | rtems_vector_number vector = UINT32_MAX; |
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185 | |
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186 | if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_NOT_INITIALIZED) { |
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187 | lpc24xx_ssp_dma_status status = LPC24XX_SSP_DMA_INVALID; |
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188 | |
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189 | /* Test and set DMA support status */ |
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190 | rtems_interrupt_disable(level); |
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191 | status = lpc24xx_ssp_dma_data.status; |
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192 | if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) { |
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193 | lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_INITIALIZATION; |
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194 | } |
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195 | rtems_interrupt_enable(level); |
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196 | |
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197 | if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) { |
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198 | /* Install DMA interrupt handler */ |
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199 | sc = rtems_interrupt_handler_install( |
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200 | LPC24XX_IRQ_DMA, |
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201 | "SSP DMA", |
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202 | RTEMS_INTERRUPT_SHARED, |
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203 | lpc24xx_ssp_dma_handler, |
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204 | &lpc24xx_ssp_dma_data |
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205 | ); |
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206 | RTEMS_CHECK_SC(sc, "install DMA interrupt handler"); |
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207 | |
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208 | /* Set DMA support status */ |
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209 | lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_AVAILABLE; |
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210 | } |
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211 | } |
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212 | |
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213 | /* Disable module */ |
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214 | regs->cr1 = 0; |
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215 | |
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216 | /* Set clock select and get vector number */ |
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217 | switch ((uintptr_t) regs) { |
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218 | case SSP0_BASE_ADDR: |
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219 | rtems_interrupt_disable(level); |
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220 | PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0(PCLKSEL1, 1); |
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221 | rtems_interrupt_enable(level); |
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222 | |
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223 | vector = LPC24XX_IRQ_SPI_SSP_0; |
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224 | break; |
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225 | case SSP1_BASE_ADDR: |
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226 | rtems_interrupt_disable(level); |
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227 | PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1(PCLKSEL0, 1); |
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228 | rtems_interrupt_enable(level); |
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229 | |
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230 | vector = LPC24XX_IRQ_SSP_1; |
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231 | break; |
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232 | default: |
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233 | return RTEMS_IO_ERROR; |
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234 | } |
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235 | |
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236 | /* Set serial clock rate to save value */ |
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237 | regs->cr0 = SET_SSP_CR0_SCR(0, 255); |
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238 | |
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239 | /* Set clock prescaler */ |
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240 | if (pre > 254) { |
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241 | pre = 254; |
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242 | } else if (pre < 2) { |
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243 | pre = 2; |
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244 | } |
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245 | regs->cpsr = pre; |
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246 | |
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247 | /* Save clock value */ |
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248 | e->clock = pclk / pre; |
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249 | |
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250 | /* Enable module and loop back mode */ |
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251 | regs->cr1 = SSP_CR1_LBM | SSP_CR1_SSE; |
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252 | |
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253 | /* Install interrupt handler */ |
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254 | sc = rtems_interrupt_handler_install( |
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255 | vector, |
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256 | "SSP", |
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257 | RTEMS_INTERRUPT_UNIQUE, |
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258 | lpc24xx_ssp_handler, |
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259 | e |
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260 | ); |
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261 | RTEMS_CHECK_SC(sc, "install interrupt handler"); |
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262 | |
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263 | /* Enable receiver overrun interrupts */ |
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264 | e->regs->imsc = SSP_IMSC_RORIM; |
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265 | |
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266 | return RTEMS_SUCCESSFUL; |
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267 | } |
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268 | |
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269 | static rtems_status_code lpc24xx_ssp_send_start(rtems_libi2c_bus_t *bus) |
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270 | { |
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271 | return RTEMS_SUCCESSFUL; |
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272 | } |
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273 | |
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274 | static rtems_status_code lpc24xx_ssp_send_stop(rtems_libi2c_bus_t *bus) |
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275 | { |
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276 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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277 | |
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278 | /* Release DMA support */ |
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279 | if (lpc24xx_ssp_dma_data.bus == e) { |
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280 | if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_AVAILABLE) { |
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281 | lpc24xx_dma_channel_release(0); |
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282 | lpc24xx_dma_channel_release(1); |
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283 | lpc24xx_ssp_dma_data.bus = NULL; |
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284 | } else { |
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285 | return RTEMS_RESOURCE_IN_USE; |
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286 | } |
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287 | } |
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288 | |
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289 | return RTEMS_SUCCESSFUL; |
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290 | } |
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291 | |
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292 | static rtems_status_code lpc24xx_ssp_send_addr( |
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293 | rtems_libi2c_bus_t *bus, |
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294 | uint32_t addr, |
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295 | int rw |
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296 | ) |
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297 | { |
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298 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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299 | |
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300 | if (lpc24xx_ssp_is_busy(e)) { |
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301 | return RTEMS_RESOURCE_IN_USE; |
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302 | } |
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303 | |
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304 | return RTEMS_SUCCESSFUL; |
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305 | } |
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306 | |
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307 | static int lpc24xx_ssp_set_transfer_mode( |
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308 | rtems_libi2c_bus_t *bus, |
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309 | const rtems_libi2c_tfr_mode_t *mode |
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310 | ) |
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311 | { |
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312 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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313 | volatile lpc24xx_ssp *regs = e->regs; |
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314 | unsigned clk = e->clock; |
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315 | unsigned br = mode->baudrate; |
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316 | unsigned scr = (clk + br - 1) / br; |
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317 | |
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318 | if (lpc24xx_ssp_is_busy(e)) { |
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319 | return -RTEMS_RESOURCE_IN_USE; |
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320 | } |
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321 | |
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322 | if (mode->bits_per_char != 8) { |
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323 | return -RTEMS_INVALID_NUMBER; |
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324 | } |
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325 | |
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326 | if (mode->lsb_first) { |
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327 | return -RTEMS_INVALID_NUMBER; |
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328 | } |
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329 | |
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330 | if (br == 0) { |
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331 | return -RTEMS_INVALID_NUMBER; |
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332 | } |
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333 | |
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334 | /* Compute new prescaler if necessary */ |
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335 | if (scr > 256 || scr < 1) { |
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336 | unsigned pre = regs->cpsr; |
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337 | unsigned pclk = clk * pre; |
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338 | |
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339 | while (scr > 256) { |
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340 | if (pre > 252) { |
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341 | return -RTEMS_INVALID_NUMBER; |
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342 | } |
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343 | pre += 2; |
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344 | clk = pclk / pre; |
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345 | scr = (clk + br - 1) / br; |
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346 | } |
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347 | |
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348 | while (scr < 1) { |
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349 | if (pre < 4) { |
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350 | return -RTEMS_INVALID_NUMBER; |
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351 | } |
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352 | pre -= 2; |
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353 | clk = pclk / pre; |
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354 | scr = (clk + br - 1) / br; |
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355 | } |
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356 | |
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357 | regs->cpsr = pre; |
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358 | e->clock = clk; |
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359 | } |
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360 | |
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361 | /* Adjust SCR */ |
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362 | --scr; |
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363 | |
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364 | e->idle_char = mode->idle_char; |
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365 | |
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366 | while (IS_FLAG_CLEARED(regs->sr, SSP_SR_TFE)) { |
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367 | /* Wait */ |
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368 | } |
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369 | |
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370 | regs->cr0 = SET_SSP_CR0_DSS(0, 0x7) |
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371 | | SET_SSP_CR0_SCR(0, scr) |
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372 | | (mode->clock_inv ? SSP_CR0_CPOL : 0) |
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373 | | (mode->clock_phs ? SSP_CR0_CPHA : 0); |
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374 | |
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375 | return 0; |
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376 | } |
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377 | |
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378 | static int lpc24xx_ssp_read_write( |
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379 | rtems_libi2c_bus_t *bus, |
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380 | unsigned char *in, |
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381 | const unsigned char *out, |
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382 | int n |
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383 | ) |
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384 | { |
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385 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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386 | volatile lpc24xx_ssp *regs = e->regs; |
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387 | int r = 0; |
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388 | int w = 0; |
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389 | int dr = 1; |
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390 | int dw = 1; |
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391 | int m = 0; |
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392 | uint32_t sr = regs->sr; |
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393 | unsigned char trash = 0; |
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394 | unsigned char idle_char = (unsigned char) e->idle_char; |
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395 | |
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396 | if (lpc24xx_ssp_is_busy(e)) { |
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397 | return -RTEMS_RESOURCE_IN_USE; |
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398 | } |
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399 | |
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400 | if (n < 0) { |
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401 | return -RTEMS_INVALID_SIZE; |
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402 | } |
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403 | |
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404 | /* Disable DMA on SSP */ |
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405 | regs->dmacr = 0; |
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406 | |
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407 | if (in == NULL) { |
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408 | dr = 0; |
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409 | in = &trash; |
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410 | } |
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411 | |
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412 | if (out == NULL) { |
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413 | dw = 0; |
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414 | out = &idle_char; |
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415 | } |
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416 | |
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417 | /* |
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418 | * Assumption: The transmit and receive FIFOs are empty. If this assumption |
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419 | * is not true an input buffer overflow may occur or we may never exit the |
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420 | * loop due to data loss. This is only possible if entities external to this |
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421 | * driver operate on the SSP. |
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422 | */ |
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423 | |
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424 | while (w < n) { |
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425 | /* FIFO capacity */ |
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426 | m = w - r; |
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427 | |
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428 | /* Write */ |
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429 | if (IS_FLAG_SET(sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) { |
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430 | regs->dr = *out; |
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431 | ++w; |
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432 | out += dw; |
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433 | } |
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434 | |
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435 | /* Read */ |
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436 | if (IS_FLAG_SET(sr, SSP_SR_RNE)) { |
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437 | *in = (unsigned char) regs->dr; |
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438 | ++r; |
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439 | in += dr; |
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440 | } |
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441 | |
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442 | /* New status */ |
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443 | sr = regs->sr; |
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444 | } |
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445 | |
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446 | /* Read outstanding input */ |
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447 | while (r < n) { |
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448 | /* Wait */ |
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449 | do { |
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450 | sr = regs->sr; |
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451 | } while (IS_FLAG_CLEARED(sr, SSP_SR_RNE)); |
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452 | |
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453 | /* Read */ |
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454 | *in = (unsigned char) regs->dr; |
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455 | ++r; |
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456 | in += dr; |
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457 | } |
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458 | |
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459 | return n; |
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460 | } |
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461 | |
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462 | static int lpc24xx_ssp_read_write_async( |
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463 | rtems_libi2c_bus_t *bus, |
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464 | unsigned char *in, |
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465 | const unsigned char *out, |
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466 | int n, |
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467 | rtems_libi2c_read_write_done_t done, |
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468 | void *arg |
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469 | ) |
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470 | { |
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471 | rtems_interrupt_level level; |
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472 | lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus; |
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473 | volatile lpc24xx_ssp *ssp = e->regs; |
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474 | volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR(0); |
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475 | volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR(1); |
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476 | uint32_t di = GPDMA_CH_CTRL_DI; |
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477 | uint32_t si = GPDMA_CH_CTRL_SI; |
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478 | |
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479 | if (n < 0 || n > (int) GPDMA_CH_CTRL_TSZ_MAX) { |
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480 | return -RTEMS_INVALID_SIZE; |
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481 | } |
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482 | |
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483 | /* Try to reserve DMA support for this bus */ |
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484 | if (lpc24xx_ssp_dma_data.bus == NULL) { |
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485 | rtems_interrupt_disable(level); |
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486 | if (lpc24xx_ssp_dma_data.bus == NULL) { |
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487 | lpc24xx_ssp_dma_data.bus = e; |
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488 | } |
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489 | rtems_interrupt_enable(level); |
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490 | |
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491 | /* Try to obtain DMA channels */ |
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492 | if (lpc24xx_ssp_dma_data.bus == e) { |
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493 | rtems_status_code cs0 = lpc24xx_dma_channel_obtain(0); |
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494 | rtems_status_code cs1 = lpc24xx_dma_channel_obtain(1); |
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495 | |
---|
496 | if (cs0 != RTEMS_SUCCESSFUL || cs1 != RTEMS_SUCCESSFUL) { |
---|
497 | if (cs0 == RTEMS_SUCCESSFUL) { |
---|
498 | lpc24xx_dma_channel_release(0); |
---|
499 | } |
---|
500 | if (cs1 == RTEMS_SUCCESSFUL) { |
---|
501 | lpc24xx_dma_channel_release(1); |
---|
502 | } |
---|
503 | lpc24xx_ssp_dma_data.bus = NULL; |
---|
504 | } |
---|
505 | } |
---|
506 | } |
---|
507 | |
---|
508 | /* Check if DMA support is available */ |
---|
509 | if (lpc24xx_ssp_dma_data.bus != e |
---|
510 | || lpc24xx_ssp_dma_data.status != LPC24XX_SSP_DMA_AVAILABLE) { |
---|
511 | return -RTEMS_RESOURCE_IN_USE; |
---|
512 | } |
---|
513 | |
---|
514 | /* Set DMA support status and parameter */ |
---|
515 | lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_WAIT; |
---|
516 | lpc24xx_ssp_dma_data.done = done; |
---|
517 | lpc24xx_ssp_dma_data.n = n; |
---|
518 | lpc24xx_ssp_dma_data.arg = arg; |
---|
519 | |
---|
520 | /* Enable DMA on SSP */ |
---|
521 | ssp->dmacr = SSP_DMACR_RXDMAE | SSP_DMACR_TXDMAE; |
---|
522 | |
---|
523 | /* Receive */ |
---|
524 | if (in != NULL) { |
---|
525 | receive_channel->desc.dest = (uint32_t) in; |
---|
526 | } else { |
---|
527 | receive_channel->desc.dest = (uint32_t) &lpc24xx_ssp_trash; |
---|
528 | di = 0; |
---|
529 | } |
---|
530 | receive_channel->desc.src = (uint32_t) &ssp->dr; |
---|
531 | receive_channel->desc.lli = 0; |
---|
532 | receive_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n) |
---|
533 | | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4) |
---|
534 | | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4) |
---|
535 | | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8) |
---|
536 | | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8) |
---|
537 | | GPDMA_CH_CTRL_ITC |
---|
538 | | di; |
---|
539 | receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER(0, GPDMA_CH_CFG_PER_SSP1_RX) |
---|
540 | | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA) |
---|
541 | | GPDMA_CH_CFG_IE |
---|
542 | | GPDMA_CH_CFG_ITC |
---|
543 | | GPDMA_CH_CFG_EN; |
---|
544 | |
---|
545 | /* Transmit */ |
---|
546 | if (out != NULL) { |
---|
547 | transmit_channel->desc.src = (uint32_t) out; |
---|
548 | } else { |
---|
549 | transmit_channel->desc.src = (uint32_t) &e->idle_char; |
---|
550 | si = 0; |
---|
551 | } |
---|
552 | transmit_channel->desc.dest = (uint32_t) &ssp->dr; |
---|
553 | transmit_channel->desc.lli = 0; |
---|
554 | transmit_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n) |
---|
555 | | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4) |
---|
556 | | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4) |
---|
557 | | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8) |
---|
558 | | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8) |
---|
559 | | GPDMA_CH_CTRL_ITC |
---|
560 | | si; |
---|
561 | transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER(0, GPDMA_CH_CFG_PER_SSP1_TX) |
---|
562 | | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA) |
---|
563 | | GPDMA_CH_CFG_IE |
---|
564 | | GPDMA_CH_CFG_ITC |
---|
565 | | GPDMA_CH_CFG_EN; |
---|
566 | |
---|
567 | return 0; |
---|
568 | } |
---|
569 | |
---|
570 | static int lpc24xx_ssp_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n) |
---|
571 | { |
---|
572 | return lpc24xx_ssp_read_write(bus, in, NULL, n); |
---|
573 | } |
---|
574 | |
---|
575 | static int lpc24xx_ssp_write( |
---|
576 | rtems_libi2c_bus_t *bus, |
---|
577 | unsigned char *out, |
---|
578 | int n |
---|
579 | ) |
---|
580 | { |
---|
581 | return lpc24xx_ssp_read_write(bus, NULL, out, n); |
---|
582 | } |
---|
583 | |
---|
584 | static int lpc24xx_ssp_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) |
---|
585 | { |
---|
586 | int rv = -1; |
---|
587 | const rtems_libi2c_tfr_mode_t *tm = (const rtems_libi2c_tfr_mode_t *) arg; |
---|
588 | rtems_libi2c_read_write_t *rw = (rtems_libi2c_read_write_t *) arg; |
---|
589 | rtems_libi2c_read_write_async_t *rwa = |
---|
590 | (rtems_libi2c_read_write_async_t *) arg; |
---|
591 | |
---|
592 | switch (cmd) { |
---|
593 | case RTEMS_LIBI2C_IOCTL_READ_WRITE: |
---|
594 | rv = lpc24xx_ssp_read_write(bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt); |
---|
595 | break; |
---|
596 | case RTEMS_LIBI2C_IOCTL_READ_WRITE_ASYNC: |
---|
597 | rv = lpc24xx_ssp_read_write_async( |
---|
598 | bus, |
---|
599 | rwa->rd_buf, |
---|
600 | rwa->wr_buf, |
---|
601 | rwa->byte_cnt, |
---|
602 | rwa->done, |
---|
603 | rwa->arg |
---|
604 | ); |
---|
605 | break; |
---|
606 | case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: |
---|
607 | rv = lpc24xx_ssp_set_transfer_mode(bus, tm); |
---|
608 | break; |
---|
609 | default: |
---|
610 | rv = -RTEMS_NOT_DEFINED; |
---|
611 | break; |
---|
612 | } |
---|
613 | |
---|
614 | return rv; |
---|
615 | } |
---|
616 | |
---|
617 | static const rtems_libi2c_bus_ops_t lpc24xx_ssp_ops = { |
---|
618 | .init = lpc24xx_ssp_init, |
---|
619 | .send_start = lpc24xx_ssp_send_start, |
---|
620 | .send_stop = lpc24xx_ssp_send_stop, |
---|
621 | .send_addr = lpc24xx_ssp_send_addr, |
---|
622 | .read_bytes = lpc24xx_ssp_read, |
---|
623 | .write_bytes = lpc24xx_ssp_write, |
---|
624 | .ioctl = lpc24xx_ssp_ioctl |
---|
625 | }; |
---|
626 | |
---|
627 | static lpc24xx_ssp_bus_entry lpc24xx_ssp_bus_table [LPC24XX_SSP_NUMBER] = { |
---|
628 | { |
---|
629 | /* SSP 0 */ |
---|
630 | .bus = { |
---|
631 | .ops = &lpc24xx_ssp_ops, |
---|
632 | .size = sizeof(lpc24xx_ssp_bus_entry) |
---|
633 | }, |
---|
634 | .regs = (volatile lpc24xx_ssp *) SSP0_BASE_ADDR, |
---|
635 | .clock = 0, |
---|
636 | .idle_char = 0xffffffff |
---|
637 | }, { |
---|
638 | /* SSP 1 */ |
---|
639 | .bus = { |
---|
640 | .ops = &lpc24xx_ssp_ops, |
---|
641 | .size = sizeof(lpc24xx_ssp_bus_entry) |
---|
642 | }, |
---|
643 | .regs = (volatile lpc24xx_ssp *) SSP1_BASE_ADDR, |
---|
644 | .clock = 0, |
---|
645 | .idle_char = 0xffffffff |
---|
646 | } |
---|
647 | }; |
---|
648 | |
---|
649 | rtems_libi2c_bus_t * const lpc24xx_ssp_0 = |
---|
650 | (rtems_libi2c_bus_t *) &lpc24xx_ssp_bus_table [0]; |
---|
651 | |
---|
652 | rtems_libi2c_bus_t * const lpc24xx_ssp_1 = |
---|
653 | (rtems_libi2c_bus_t *) &lpc24xx_ssp_bus_table [1]; |
---|