1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx_clocks |
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5 | * |
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6 | * @brief System clocks. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <rtems/counter.h> |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <bsp/lpc24xx.h> |
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27 | #include <bsp/system-clocks.h> |
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28 | |
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29 | /** |
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30 | * @brief Internal RC oscillator frequency in [Hz]. |
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31 | */ |
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32 | #define LPC24XX_OSCILLATOR_INTERNAL 4000000U |
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33 | |
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34 | #ifndef LPC24XX_OSCILLATOR_MAIN |
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35 | #error "unknown main oscillator frequency" |
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36 | #endif |
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37 | |
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38 | #ifndef LPC24XX_OSCILLATOR_RTC |
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39 | #error "unknown RTC oscillator frequency" |
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40 | #endif |
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41 | |
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42 | void lpc24xx_timer_initialize(void) |
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43 | { |
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44 | /* Reset timer */ |
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45 | T1TCR = TCR_RST; |
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46 | |
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47 | /* Set timer mode */ |
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48 | T1CTCR = 0; |
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49 | |
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50 | /* Set prescaler to zero */ |
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51 | T1PR = 0; |
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52 | |
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53 | /* Reset all interrupt flags */ |
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54 | T1IR = 0xff; |
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55 | |
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56 | /* Do not stop on a match */ |
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57 | T1MCR = 0; |
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58 | |
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59 | /* No captures */ |
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60 | T1CCR = 0; |
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61 | |
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62 | /* Start timer */ |
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63 | T1TCR = TCR_EN; |
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64 | |
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65 | rtems_counter_initialize_converter(LPC24XX_PCLK); |
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66 | } |
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67 | |
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68 | CPU_Counter_ticks _CPU_Counter_read(void) |
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69 | { |
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70 | return lpc24xx_timer(); |
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71 | } |
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72 | |
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73 | void lpc24xx_micro_seconds_delay(unsigned us) |
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74 | { |
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75 | unsigned start = lpc24xx_timer(); |
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76 | unsigned delay = us * (LPC24XX_PCLK / 1000000); |
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77 | unsigned elapsed = 0; |
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78 | |
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79 | do { |
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80 | elapsed = lpc24xx_timer() - start; |
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81 | } while (elapsed < delay); |
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82 | } |
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83 | |
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84 | #ifdef ARM_MULTILIB_ARCH_V7M |
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85 | unsigned lpc17xx_sysclk(unsigned clksrcsel) |
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86 | { |
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87 | return (clksrcsel & LPC17XX_SCB_CLKSRCSEL_CLKSRC) != 0 ? |
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88 | LPC24XX_OSCILLATOR_MAIN |
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89 | : LPC24XX_OSCILLATOR_INTERNAL; |
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90 | } |
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91 | #endif |
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92 | |
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93 | unsigned lpc24xx_pllclk(void) |
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94 | { |
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95 | #ifdef ARM_MULTILIB_ARCH_V4 |
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96 | unsigned clksrc = GET_CLKSRCSEL_CLKSRC(CLKSRCSEL); |
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97 | unsigned pllinclk = 0; |
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98 | unsigned pllclk = 0; |
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99 | |
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100 | /* Get PLL input frequency */ |
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101 | switch (clksrc) { |
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102 | case 0: |
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103 | pllinclk = LPC24XX_OSCILLATOR_INTERNAL; |
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104 | break; |
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105 | case 1: |
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106 | pllinclk = LPC24XX_OSCILLATOR_MAIN; |
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107 | break; |
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108 | case 2: |
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109 | pllinclk = LPC24XX_OSCILLATOR_RTC; |
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110 | break; |
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111 | default: |
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112 | return 0; |
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113 | } |
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114 | |
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115 | /* Get PLL output frequency */ |
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116 | if ((PLLSTAT & PLLSTAT_PLLC) != 0) { |
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117 | uint32_t pllcfg = PLLCFG; |
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118 | unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1; |
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119 | unsigned m = GET_PLLCFG_MSEL(pllcfg) + 1; |
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120 | |
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121 | pllclk = (pllinclk / n) * 2 * m; |
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122 | } else { |
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123 | pllclk = pllinclk; |
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124 | } |
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125 | #else |
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126 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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127 | unsigned sysclk = lpc17xx_sysclk(scb->clksrcsel); |
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128 | unsigned pllstat = scb->pll_0.stat; |
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129 | unsigned pllclk = 0; |
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130 | unsigned enabled_and_locked = LPC17XX_PLL_STAT_PLLE |
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131 | | LPC17XX_PLL_STAT_PLOCK; |
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132 | |
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133 | if ((pllstat & enabled_and_locked) == enabled_and_locked) { |
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134 | unsigned m = LPC17XX_PLL_SEL_MSEL_GET(pllstat) + 1; |
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135 | |
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136 | pllclk = sysclk * m; |
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137 | } |
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138 | #endif |
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139 | |
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140 | return pllclk; |
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141 | } |
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142 | |
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143 | unsigned lpc24xx_cclk(void) |
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144 | { |
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145 | #ifdef ARM_MULTILIB_ARCH_V4 |
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146 | /* Get PLL output frequency */ |
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147 | unsigned pllclk = lpc24xx_pllclk(); |
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148 | |
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149 | /* Get CPU frequency */ |
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150 | unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1); |
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151 | #else |
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152 | volatile lpc17xx_scb *scb = &LPC17XX_SCB; |
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153 | unsigned cclksel = scb->cclksel; |
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154 | unsigned cclk_in = 0; |
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155 | unsigned cclk = 0; |
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156 | |
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157 | if ((cclksel & LPC17XX_SCB_CCLKSEL_CCLKSEL) != 0) { |
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158 | cclk_in = lpc24xx_pllclk(); |
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159 | } else { |
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160 | cclk_in = lpc17xx_sysclk(scb->clksrcsel); |
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161 | } |
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162 | |
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163 | cclk = cclk_in / LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(cclksel); |
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164 | #endif |
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165 | |
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166 | return cclk; |
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167 | } |
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